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82C55A Datasheet, PDF (8/26 Pages) Intel Corporation – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE | |||
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82C55A
Mode 0 Conï¬gurations (Continued)
CONTROL WORD #12
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 0 0
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 1 0
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 0 1
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
10 0 1 1 0 1 1
A
82C55A
D7 - D0
C
B
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
Operating Modes
Mode 1 - (Strobed Input/Output). This functional conï¬gura-
tion provides a means for transferring I/O data to or from a
speciï¬ed port in conjunction with strobes or âhand shakingâ
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these âhand shakingâ signals.
Mode 1 Basic Function Deï¬nitions:
⢠Two Groups (Group A and Group B)
⢠Each group contains one 8-bit port and one 4-bit
control/data port
⢠The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
⢠The 4-bit port is used for control and status of the 8-bit
port.
Input Control Signal Deï¬nition
(Figures 6 and 7)
STB (Strobe Input)
A âlowâ on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A âhighâ on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg-
ment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.
MODE 1 (PORT A)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0
PC6, PC7
1 = INPUT
0 = OUTPUT
RD
PA7-PA0
INTE
PC4
A
PC5
8
STBA
IBFA
PC3
PC6, PC7
INTRA
2
I/O
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
11
MODE 1 (PORT B)
PB7-PB0
INTE
PC2
B
PC1
8
STBB
IBFB
PC0
INTRB
RD
FIGURE 6. MODE 1 INPUT
8
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