X9110_08 Datasheet, PDF (7/18 Pages) Intersil Corporation – Dual Supply/Low Power/1024-Tap/SPI Bus

X9110
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (See Figure 4).
Power-up and Down Requirements
At all times, the V+ voltage must be greater than or equal to
the voltage at R_H or R_L, and the voltage at R_H or R_L must be
greater than or equal to the voltage at V-. During power-up
and power-down, V_CC, V+, and V- must reach their final
values within 1msec of each other.
CS
SCK
SI
0 1 0 100
0
00
ID3 ID2 ID1 ID0 0 0 A0 R/W I2 I1 I0
RB RA 0 0
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION REGISTER
OPCODE
ADDRESS
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0 1 0 1 00
0
0 X X 0 0 X X XX X X
ID3 ID2 ID1 ID0 0 A0 R/W I2 I1 I0 0 RB RA 0 0
DEVICE ID
INTERNAL INSTRUCTION REGISTER
ADDRESS OPCODE ADDRESS
WW W W WWW W W W
CC C C CCC C C C
RR R R RRR R R R
98 7 6 543 2 1 0
WIPER
POSITION
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
CS
SCK
SI
0 1 0 1 00
1
0 X X 0 0 X X X X X X XX 0 0 0 0 0 00
ID3 ID2 ID1 ID0 0 0 A0 R/W I2 I1 I0 0 RB RA 0 0
WIP
DEVICE ID
INTERNAL INSTRUCTION REGISTER
ADDRESS OPCODE ADDRESS
STATUS
BIT
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
7
FN8158.3
February 13, 2008