X9110_08 Datasheet, PDF (11/18 Pages) Intersil Corporation – Dual Supply/Low Power/1024-Tap/SPI Bus

X9110
D.C. Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
I_CC1
I_CC2
I_SB
V_CC Supply Current
(active)
V_CC Supply Current
(nonvolatile write)
V_CC Current (standby)
I_LI
I_LO
V_IH
V_IL
V_OL
V_OH
V_OH
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
f_SCK = 2.5 MHz, SO = Open, V_CC = 5.5V
Other Inputs = V_SS
f_SCK = 2.5MHz, SO = Open, V_CC = 5.5V
Other Inputs = V_SS
SCK = SI = V_SS, Addr. = V_SS,
CS = V_CC = 5.5V
V_IN = V_SS to V_CC
V_OUT = V_SS to V_CC
I_OL = 3mA
I_OH = -1mA, V_CC ≥ +3V
I_OH = -0.4mA, V_CC ≤ +3V
V_CC x 0.7
-1
V_CC - 0.8
V_CC - 0.4
TYP
1
MAX
(Note 13)
400
5
3
10
10
V_CC + 1
V_CC x 0.3
0.4
UNITS
µA
mA
µA
µA
µA
V
V
V
V
V
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNITS
Data changes per bit per register
years
Capacitance
SYMBOL
TEST
C_IN/OUT (Notes 8, 10) Input/Output Capacitance (SI)
C_OUT (Note 10)
Output Capacitance (SO)
C_IN (Note 10)
Input Capacitance (A0, CS, WP, HOLD, and SCK)
TEST CONDITIONS
V_OUT = 0V
V_OUT = 0V
V_IN = 0V
MAX
8
8
6
UNITS
pF
pF
pF
Power-up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
t_r V_CC (Note 10)
V_CC Power-up Rate
0.2
50
V/ms
t_PUR (Notes 10, 11) Power-up to Initiation of Read Operation
1
ms
t_PUW (Note 11)
Power-up to Initiation of Write Operation
50
ms
NOTES:
10. Limits established by characterization and are not production tested.
11. t_PUR and t_PUW are the delays required from the time the (last) power supply (V_CC-) is stable until the specific instruction can be issued.
12. ESD Rating on R_H, R_L, R_W pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
13. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
A.C. Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
11
FN8158.3
February 13, 2008