SP600 Datasheet, PDF (7/7 Pages) Intersil Corporation – Half Bridge 500VDC Driver

SP600
Functional Description
The SP600 provides a flexible, digitally controlled power
function which is intended to be used as PWM drivers of
N-Channel MOSFETs and/or IGBTs for up to 240VAC line
rectified totem-pole applications. The CMOS driveable
inputs are filtered and captured by the control logic to deter-
mine the output state. The logic includes fixed timing to pro-
hibit simultaneous conduction of the external power switches
and, thru the V_OUT sense detector, verifies the output volt-
age state is in agreement with the controlled inputs. The
>11V_DC floating power supply required to drive the upper rail
external power device is created and managed by the HVIC
through C_F and D_F. This capacitor is refreshed from the V_DD
supply each time V_OUT goes low. If the upper channel is
commanded on for a long period of time, the bootstrap
capacitor CF is automatically refreshed by bringing V_OUT
low. This is accomplished by turning off the upper rail MOS-
FET/IGBT, momentarily turning on the lower rail output
device, followed by returning control back to the upper
switch. Otherwise, C_F would gradually deplete its charge
allowing the upper switch to come out of saturation. The
upper and lower gate drivers allow for controlled charge and
discharge rates as well as facilitate the use of nearly lossless
current sensing power MOS devices. The over current trip
level can be boosted 30% on a pulse by pulse basis by logic
level ‘1’ applied to I_TRIPSELECT. A FAULT output signal is
generated when any of the following occurs:
V bias is low
Over current is detected
V phase doesn’t agree with the input signal
Reset of FAULT is provided by externally removing power or
by holding both TOP and BOT inputs low for the required
reset time (trt_MAX).
Each application can be individually optimized by the selec-
tion of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (R_C) and discharge
(R_D) impedance chosen per the load capacitance, frequency
of operation, and D_I/D_T dependent recovery characteristics
of the associated FBDs. R_D should also be sized to prevent
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (t_{OFF MIN}).
The selection of over current detection resistors (R_P), com-
patible with current sense MOSFETs/IGBTs or shunt(s) may
be used.
For the floating bootstrap supply D_F and C_F must be deter-
mined. D_F must support the worse case system bus voltage
and handle the charging currents of C_F. Proper selection
should take into consideration T_RR and T_FR per the desired
operating frequency. Proper selection of C_F is a trade off
between the minimum t_ON time of the lower rail to charge up
the capacitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350µs TYP (or even sooner if input com-
mands the TOP to switch at a faster repetition rate).
The local filter capacitor (C_DD) should be sized sufficiently
large enough to transfer the charge to C_F without causing a
significant droop in V_DD. As a rule of thumb it should be at
least 10 times larger than C_F and be located adjacent to the
V_DD and V_SS pins to minimize series resistance and
inductance.
Refer to Application Note AN8829 for more details about module operation and selection of external components.
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