ISL78419 Datasheet, PDF (7/20 Pages) Intersil Corporation – Integrated Automotive TFT-LCD Power Supply Regulator

ISL78419
Electrical Specifications V_IN = ENABLE = 3.3V, A_VDD = 8V, V_LDO = 2.5V, V_ON = 24V, V_OFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +105°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6) UNITS
I_SC
Output Short Circuit Current
Pull-up
Pull-down
150
225
mA
150
200
mA
SR
Slew Rate
25
V/µs
BW
Gain Bandwidth
-3dB gain point
20
MHz
DIGITAL CONTROLLED POTENTIOMETER
SET_VR
SET Voltage Resolution
(Note 12)
8
Bits
SET_DNL SET Differential Nonlinearity
(Notes 8, 9, 14)
T_A = +25°C
±1
LSB
SET_ZSE SET Zero-Scale Error
(Notes 10, 14)
T_A = +25°C
±2
LSB
SET_FSE SET Full-Scale Error
(Notes 11, 14)
T_A = +25°C
±8
LSB
I_RSET
RSET Current
AVDD to SET AVDD to SET Voltage Attenuation
1:20
100
µA
V/V
FAULT DETECTION THRESHOLD
V_UVLO
Undervoltage Lock out Threshold
OVP_AVDD Boost Overvoltage Protection Off
(Note 13) Threshold to Shutdown IC
PV_IN rising
PV_IN falling
2.25
2.125
15.0
2.33
2.20
15.5
2.41
V
2.27
V
16.0
V
T_OFF
Thermal Shut-Down all Channels
POWER SEQUENCE TIMING
Temperature rising
153
°C
t_ssVLOGIC
I_ss
VLOGIC Soft-start Time
Boost Soft-start Current
0.45
ms
3
5.5
8
µA
Serial Interface Specifications For SCL and SDA Unless Otherwise Noted.
SYMBOL
PARAMETER
f_SCL SCL Frequency
(Note 6)
t_iN
Pulse Width Suppression Time at SDA
(Note 6) and SCL Inputs
t_AA SCL Falling Edge to SDA Output Data
Valid
t_BUF Time the Bus Must be Free Before the
Start of a New Transmission
t_LOW
t_HIGH
t_SU:STA
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
t_HD:STA START Condition Hold Time
TEST CONDITIONS
Any pulse narrower than the maximum
specification is suppressed
SCL falling edge crossing 30% of V_IN, until
SDA exits the 30% to 70% of V_IN window
SDA crossing 70% of V_CC during a STOP
condition, to SDA crossing 70% of V_IN during
the following START condition
Measured at the 30% of V_IN crossing
Measured at the 70% of V_IN crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V_IN
From SDA falling edge crossing 30% of V_IN to
SCL falling edge crossing 70% of V_IN
MIN
(Note 14)
480
480
400
480
400
TYP
(Note 7)
MAX
(Note 14) UNITS
400
kHz
50
ns
480
ns
ns
ns
ns
ns
ns
7
FN8292.1
December 3, 2012