ISL78419 Datasheet, PDF (2/20 Pages) Intersil Corporation – Integrated Automotive TFT-LCD Power Supply Regulator

Application Diagram
ISL78419
VIN
C1, 2
20µF
C32
VIN
0.1µF
VLOGIC
VLOGIC
LDO VIN
C25
1µF
C24
2.2µF
R18
3.92kΩ
R17
8.25kΩ
AVDD
C19
0.47µF
R9
10kΩ
133kΩ
R8
R7
83kΩ
VCOM
VIN
EN
SS
FREQ
SEQUENCER
L _IN
L _OUT
LDO
AVDD BOOST
CONTROLLER
ADJ
SCL
SDA
RSET
POS
DCP
GPM
AVDD
OUT
NEG
VCOM OP
VOLTAGE
DETECTOR
THERMAL PAD
L1 10µH
LX
PGND
D1 _{C4, 5, 6}
30µF
SW
R1
73.2kΩ
AVDD
C7 AVDD
0.1µF
FB
R2 8.06kΩ
COMP
R12 5.5kΩ C20 15nF
D4
Q1
VOFF
VFLK
VGH
VDPM
CE
RE
VGHM
GPM_LO
VDIV
C11
0.1µF
AVDD
C15
1µF
C8
47nF
D2 C9
1µF
C17 1nF
C14 100pF
R5 100kΩ
C18
0.47µF
R14 85kΩ
R6 1kΩ
Z1
SW
C10
47nF
D3
C16
1µF
VON
C12
1µF
C28
0.1µF
VGH GPM
R22 22kΩ
R26 100kΩ
V_IN
AVDD
VGH
CD2
RESET
OPEN
R15 115kΩ
C26 1nF
RESET
R16
10kΩ
VLOGIC
Pin Descriptions
PIN#
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
DESCRIPTION
FB AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage.
PGND Power ground
CE Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time.
RE Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate.
VGH Gate Pulse Modulator High Voltage Input. Place a 0.1µF decoupling capacitor close to the VGH pin.
VGHM Gate Pulse Modulator Output for gate driver IC
VFLK
VDPM
Gate Pulse Modulator Control input from T_CON
Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current
source charges the capacitor on VDPM.
GPM_LO Gate Pulse Modulator Low Voltage Input; place a 0.47µF decoupling capacitor close to the GPM_LO pin.
AVDD
SCL
DCP and VCOM amplifier high voltage analog supply; place a 0.47µF decoupling capacitor close to the AVDD pin.
I²C compatible clock input
2
FN8292.1
December 3, 2012