ISL6842 Datasheet, PDF (7/9 Pages) Intersil Corporation – Improved Industry Standard Single Ended Current Mode PWM Controller

ISL6842, ISL6843, ISL6844, ISL6845
V_DD - V_DD is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
I_DD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:
I_OUT = Qg × f
(EQ. 5)
To optimize noise immunity, bypass V_DD to GND with a
ceramic capacitor as close to the V_DD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Description
Features
The ISL6842, ISL6843, ISL6844, ISL6845 current mode
PWMs make an ideal choice for low-cost flyback and forward
topology applications. With its greatly improved performance
over industry standard parts, it is the obvious choice for new
designs or existing designs which require updating.
Oscillator
The ISL6842, ISL6843, ISL6844, ISL6845 controllers have a
sawtooth oscillator with a programmable frequency range to
2MHz, which can be programmed with a resistor from VREF
and a capacitor to GND on the RTCT pin. (Please refer to
Fig. 4 for the resistor and capacitance required for a given
frequency.)
Soft Start Operation
Soft start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
damps any oscillations caused by the resonant tank of the
parasitic inductances in the traces of the board and the
FET’s input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
downslope. Adding excessive slope compensation,
however, results in a control loop that behaves more as a
voltage mode controller than as current mode controller.
DOWNSLOPE
CURRENT SENSE SIGNAL
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
Slope compensation may added to the CS signal in the
following manner.
RTCT
VREF
CS
VREF
COMP
GND
FIGURE 5. SOFT START
Gate Drive
The ISL6842, ISL6843, ISL6844, ISL6845 are capable of
sourcing and sinking 1A peak current. To limit the peak
current through the IC, an optional external resistor may be
placed between the totem-pole output of the IC (OUT pin)
and the gate of the MOSFET. This small series resistor also
7
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. V_DD should be
bypassed directly to GND with good high frequency
capacitors.