ISL6627 Datasheet, PDF (7/11 Pages) Intersil Corporation – VR11.1, VR12 Compatible Synchronous Rectified Buck MOSFET Driver

ISL6627
PWM
LG
UG
LG FALL TO UG RISE PROPAGATION DELAY UG FALL TO LG RISE PROPAGATION DELAY
FIGURE 3. PROGRAMMABLE PROPAGATION DELAY
ILLUSTRATION
TABLE 1. TYPICAL DELAY PROGRAMMING RESISTOR VALUE
RESISTOR FROM RESISTOR FROM LG FALL TO
UG FALL TO
TD TO VCC
TD TO GND UG RISE DELAY LG RISE DELAY
(kΩ)
(kΩ)
(ns)
(ns)
short
-
27
23
100
-
27
18
330
-
27
15
910
-
27
7
-
Short
40
18
-
100
25
18
-
360
17
18
Floating
Floating
Adaptive
Adaptive
Power-On Reset (POR) Function
VCC voltage level is monitored at all times. Once the VCC voltage
exceeds 3.85V (typically), operation of the driver is enabled and
the PWM input signal takes control of the gate drivers. If VCC
drops below the falling threshold of 3.52V (typically), operation of
the driver is disabled.
Internal Bootstrap Device
ISL6627 features an internal bootstrap schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit. The bootstrap function is also
designed to prevent the bootstrap capacitor from overcharging
due to the large negative swing at the trailing-edge of the PHASE
node excursion. This reduces the potential for overstressing the
upper driver.
The bootstrap capacitor must have a voltage rating above the
maximum VCC voltage. Its capacitance value can be estimated
from Equation 1:
C_B
OO
T
_CAP
≥
---------^Q----^G----^A---^T---^E----------
Δ V_{B O O T _CAP}
Q_GATE=
Q_{-----G---1-----}•_----V_----C_----C_--
V_GS1
•
N_Q1
(EQ. 1)
where Q_G1 is the amount of gate charge per upper MOSFET at
V_GS1 gate-source voltage and N_Q1 is the number of control
(upper) MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive. Select results
are exemplified in Figure 4.
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency (F_SW), the output drive impedance, the layout
resistance, the selected MOSFET’s internal gate resistance and its
total gate charge (Q_G). Calculating the power dissipation in the
driver for a desired application is critical to ensure safe operation.
Exceeding the maximum allowable power dissipation level may
push the IC beyond the maximum recommended operating
junction temperature. The DFN package is more suitable for high
frequency applications. See “Layout Considerations” on page 8 for
thermal impedance improvement suggestions. The total driver
power loss, essentially MOSFETs’ gate charge and driver internal
circuitry losses, can be estimated using Equations 2 and 3,
respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
P_{Q g _Q1}
=
Q_{-----G---1-----}•_----U_----V_----C_----C_----²_-
V_GS1
•
F_SW
•
N_Q1
(EQ. 2)
P_{Q g _Q2}
=
Q_{-----G---2-----}•_----L_----V_---C_----C_----²_--
V_GS2
•
F_SW
•
N_Q2
I_DR
=
⎛
⎜
⎝
Q_{-----G---1-----}•_----U_----V_----C_----C_-----•_----N_----Q----1--
V_GS1
+
Q_{-----G---2-----}•_----L_-V---V_G---C_-S---2C_-----•_-----N_{----Q----2-⎠⎟⎞}
• F_SW + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a particular
gate to source voltage (V_GS1 and V_GS2) in the corresponding
MOSFET datasheet; I_Q is the driver’s total quiescent current with
no load at both drive outputs; N_Q1 and N_Q2 are number of upper
and lower MOSFETs, respectively; UVCC and LVCC are the drive
voltages for both upper and lower FETs, respectively. The I_Q*VCC
product is the bias power of the driver without a load.
7
FN6992.0
September 22, 2011