ISL6208C_14 Datasheet, PDF (7/11 Pages) Intersil Corporation – High Voltage Synchronous Rectified Buck MOSFET Drivers

Timing Diagram
ISL6208C
PWM
t_PDHU
t_RU
t_PDLU
2.5V
t_FU
UGATE
LGATE
t_PDLL
1V
t_FL
1V
t_RL
t_PDHL
Functional Pin Description
UGATE
The UGATE pin is the upper gate drive output. Connect to gate of
the high-side power N-Channel MOSFET.
BOOT
BOOT is the floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn on the
upper MOSFET. See “Internal Bootstrap Diode” on page 9 for
guidance in choosing the appropriate capacitor value.
PWM
The PWM signal is the control input for the driver. The PWM signal
can enter three distinct states during operation. See “Three-State
PWM Input” on page 9 for further details. Connect this pin to the
PWM output of the controller.
GND
GND is the ground pin for the IC.
LGATE
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FCCM
The FCCM pin enables or disables Diode Emulation. When FCCM
is LOW, diode emulation is allowed. Otherwise, continuous
conduction mode is forced. See “Diode Emulation” on page 9 for
more detail.
t_TSSHD
t_RU
t_FU
t_PTS
t_PTS
t_TSSHD
t_FL
PHASE
Connect the PHASE pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin provides a return path for
the upper gate driver.
Theory of Operation
Designed for speed, the ISL6208C dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower MOSFET
(see “Timing Diagram”). After a short propagation delay [t_PDLL],
the lower gate begins to fall. Typical fall times [t_FL] are provided
in the “Electrical Specifications” on page 5. Adaptive
shoot-through circuitry monitors the LGATE voltage. When LGATE
has fallen below 1V, UGATE is allowed to turn ON. This prevents
both the lower and upper MOSFETs from conducting
simultaneously, or shoot-through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay (t_PDLU) is encountered before the upper gate
begins to fall (t_FU). The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise after the upper
MOSFET gate-to-source voltage drops below 1V. The lower gate
then rises (t_RL), turning on the lower MOSFET.
This driver is optimized for converters with large step-down
compared to the upper MOSFET because the lower MOSFET
conducts for a much longer time in a switching period. The lower
gate driver is therefore sized much larger to meet this application
requirement.
The 0.5Ω ON-resistance and 4A sink current capability enables
the lower gate driver to absorb the current injected to the lower
gate through the drain-to-gate capacitor of the lower MOSFET and
prevents a shoot-through caused by the high dv/dt of the phase
node.
7
FN8395.0
November 29, 2012