ISL55141_11 Datasheet, PDF (7/14 Pages) Intersil Corporation – High-Speed 18V CMOS Comparators

ISL55141, ISL55142, ISL55143
The maximum power dissipation allowed in a package is
determined according to Equation 1.
P_DMAX = ^T----^J---^M-----^A----^X--_Θ----^-_J---_A-^T----^A----^M----^A----^X--
(EQ. 1)
where:
• T_JMAX = Maximum junction temperature
• T_AMAX = Maximum ambient temperature
• θ_JA = Thermal resistance of the package
• P_DMAX = Maximum power dissipation in the package
Approximate Power Dissipation
(Typ) P = N*[(V_CC-V_EE)*8.25mW + 90pF*(V_CC-V_EE)^2*f +
CL*(V_OH-V_OL)^2*f]
where:
N is the number of comparators in the chip
(1 for ISL55141, 2 for ISL55142 and 4 for ISL55143).
(f) is the operating frequency.
CL is the load capacitor.
The power dissipation calculated from the above formula
may have an error of ±20 to 25%.
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads.
Power also depends on the number of channels changing
state and frequency of operation. The extent of continuous
active pattern generation/reception will greatly affect
dissipation requirements.
The user should evaluate various heat sink/cooling options
in order to control the ambient temperature part of the
equation. This is especially true if the user’s applications
require continuous, high-speed operation.
Note: The reader is cautioned against assuming the same
level of thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted.
Power Supply Information
V_CC
OPTIONAL PROTECTION
DIODE
CV_A
V_OH
V_INP
CV_B
Q_A
Q_B
V_OL
V_EE
OPTIONAL PROTECTION
DIODE
Circuit design must always take into account the internal
EOS/ESD protection structure of the device.
Important Note: The QFN package metal plane is used
for heat sinking of the device. It is electrically connected
to the negative supply potential (V_EE). If V_EE is tied to
ground, the thermal pad can be connected to ground.
Otherwise, the thermal pad (V_EE) must be isolated from
other power planes.
Power Supply Sequencing
The ISL55141, ISL55142, ISL55143 reference every supply
with respect to V_EE. Therefore, apply V_EE, V_OL then V_CC
followed by the CV_A and CV_B supplies. The comparator
V_INP pin should not exceed V_EE or V_CC during power-up.
In cases where inputs may exceed voltage rails during
power-up, series resistance should be employed to
safeguard EOS to the ESD protection diodes.
7
FN6230.2
March 1, 2011