ISL54504 Datasheet, PDF (7/12 Pages) Intersil Corporation – +1.8V to +5.5V, 2.5OHM, Single SPST Analog Switches

ISL54504, ISL54505
Test Circuits and Waveforms (Continued)
V+
C
NO OR NC
IMPEDANCE
ANALYZER
IN V_INL OR V_INH
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54504 and ISL54505 are bidirectional, single
pole/single throw (SPST) analog switches. They offer
precise switching capability from a single 1.8V to 5.5V
supply with low ON-resistance (2.5Ω) and high speed
operation (t_ON = 25ns, t_OFF = 15ns). The devices are
especially well suited for portable battery powered
equipment due to their low operating supply voltage
(1.8V), low power consumption (0.15µW), low
leakage currents (300nA max) and tiny µTDFN and
SOT-23 packages.
The ISL54504 is a single normally open (NO) SPST
analog switch. The ISL54505 is a single normally
closed (NC) SPST analog switch.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the
V+ power supply pin of the ISL54504, ISL54505 IC
(see Figure 6).
During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate
currents can be generated in the IC that can trigger
parasitic SCR structures to turn ON, creating a low
impedance path from the V+ power supply to ground.
This will result in a significant amount of current flow in
the IC, which can potentially create a latch-up state or
permanently damage the IC. The external V+ resistor
limits the current during this over-stress situation and
has been found to prevent latch-up or destructive
damage for many overvoltage transient events.
Under normal operation the sub-microamp I_DD current
of the IC produces an insignificant voltage drop across
the 100Ω series resistor resulting in no impact to
switch operation or performance.
7
V+
C
OPTIONAL
PROTECTION
RESISTOR
100Ω
NO
NC
IN
GND
COM
FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED
ESD AND LATCH-UP IMMUNITY
Supply Sequencing And Overvoltage
Protection
With any CMOS device, proper power supply
sequencing is required to protect the device from
excessive input currents, which might permanently
damage the IC. All I/O pins contain ESD protection
diodes from the pin to V+ and to GND (see Figure 7).
To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed then
precautions must be implemented to prohibit the
current and voltage at the logic pin and signal pins
from exceeding the maximum ratings of the switch.
The following two methods can be used to provide
additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 7). The
resistor limits the input current below the threshold
that produces permanent damage and the sub-
FN6552.2
October 23, 2009