ISL54048_0706 Datasheet, PDF (7/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch

ISL54048, ISL54049
Test Circuits and Waveforms (Continued)
V+
C
SIGNAL
GENERATOR
NX1 OR NX2 _COM
50Ω
V+
C
NX1 OR NX2
IN₁
0V or V+
ANALYZER
R_L
COM
NX1 OR NX2
GND
N.C.
IMPEDANCE
ANALYZER
IN 0V or V+
COM
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54048 and ISL54049 are bidirectional, dual single
pole/single throw (SPST) analog switches that offer precise
switching capability from a single 1.65V to 4.5V supply with
low on-resistance (0.29Ω) and high speed operation
(t_ON = 40ns, t_OFF = 20ns). The devices are especially well
suited for portable battery powered equipment due to their
low operating supply voltage (1.65V), low power
consumption (4.5µW max), low leakage currents (195nA max)
and the tiny µTQFN package. The ultra low ON-resistance
and r_ON flatness provide very low insertion loss and distortion
to applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the IC (see Figure 7).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation the sub-microamp I_DD current of the
IC produces an insignificant voltage drop across the 100Ω
series resistor resulting in no impact to switch operation or
performance.
Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
V+
C
OPTIONAL
PROTECTION
RESISTOR
100Ω
NX
COMx
IN
GND
FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
7
FN6469.1
June 11, 2007