ISL45042A Datasheet, PDF (7/8 Pages) Intersil Corporation – LCD Module Calibrator

ISL45042A
ISL45042A Truth Table
The ISL45042A truth table is shown in Table 2. For proper
operation the CE should be disabled (pulled low) before
powering the device down to assure that the glitches and
transients will not cause unwanted EEPROM overwriting.
TABLE 2. TRUTH TABLE
INPUT
OUTPUT
CTL
CE
VDD
OUT
ICC MEMORY
Mid to Hi Hi
VDD Increment Normal
X
Mid to Lo Hi
VDD Decrement Normal
X
X
Lo
VDD No Change Increased Read
>4.9V Hi
VDD No Change Increased Program
CE_ST
.
CTL_MTC
CTL_IHRPW
CTL HIGH
CTL V_DD/2
CTL LOW
CTL_IHMPW
CTL_ILMPW
CTL_ILRPW
CE
START PROGRAMMING
COUNTER
OUTPUT ^UNDEF.
78
NOTE:
AFTER POWER IS 1ST APPLIED,
THE VERY 1ST CTL PULSE IS IGNORED
VCOM
STOP PROGRAMMING
START PROGRAMMING
79
7A
7B
7A
IGNORES 1ST PULSE
AFTER PROGRAMMING
THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING.
FIGURE 7. ISL45042A TIMING DIAGRAM
7
FN6158.4
July 9, 2008