 English |
|
|
|
|
|
|
|
| ISL45042A Datasheet, PDF (4/8 Pages) Intersil Corporation – LCD Module Calibrator | |||
| |||
| ◁ |
ISL45042A
Electrical Specifications
PARAMETER
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C (Continued)
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
MAX
TYP (Note 9) UNITS
CTL EEPROM Programming
Signal Time
CTLPT
>4.9V
Full
200
-
-
µs
Programming Time
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
PT
SETVR
SETDN
SETZSE
SETFSE
ISET
SETER
(Note 5)
Monotonic Over-Temperature
Through RSET (Note 8)
To GND, AVDD = 20V
To GND, AVDD = 4.5V
Full
-
Full
7
Full
-
Full
-
Full
-
Full
-
Full
10
Full
2.25
-
100
ms
7
7
Bits
-
±1
LSB
-
±2
LSB
-
±8
LSB
20
-
µA
-
200
kΩ
-
45
kΩ
AVDD to SET Voltage Attenuation AVDD to SET
Full
-
1:20
-
V/V
OUT Settling Time
OUTST
to ±0.5 LSB Error Band (Note 6)
Full
-
20
-
µs
OUT Voltage Range
VOUT
Full VSET + 0.5V -
13
V
OUT Voltage Drift
OUTVD
(Note 6)
25 to 55
-
<10
-
mV
NOTES:
3. CTL signal only needs to be greater than 4.9V to program EEPROM.
4. Tested at AVDD = 20V.
5. The Counter value is set to mid-scale ±4 LSBâs in the Production.
6. Simulated and Determined via Design and NOT Directly Tested.
7. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.
8. A Typical Current of 20µA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. Reference âRSET Resistorâ on page 6.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
AVDD
ISL45042A
CTL
CE
SET
OUT
RSET
ISINK
AVDD
R1
R2
+
-
VCOM
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042A has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042A sink current.
CTL Pin
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL when the CE pin is high.
COLUMN
DRIVER
SINGLE PIXEL
IN LCD PANEL
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
The output VCOM voltage is increased with a mid (VDD/2) to
high transition (0.8*VDD) on the CTL pin. The output VCOM
voltage is decreased with a mid (VDD/2) to low transition
(0.3*VDD) on the CTL pin (see Figure 7). Once the minimum
or maximum value is reached on the 128 steps, the device
will not overflow or underflow beyond that minimum or
maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200µs. The level and timing
4
FN6158.4
July 9, 2008
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese