ISL34321 Datasheet, PDF (7/13 Pages) Intersil Corporation – 16-Bit Long-Reach Video SERDES with Bi-directional Side-Channel

ISL34321
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V_,
VDD_TX = VDD_P = VDD_AN = 3.3V, T_A = +25°C, Ref_Res = 3.16kΩ, High-speed
AC-coupling capacitor = 27nF. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH SPEED RECEIVER
HS Differential Input Voltage
HS Generated Input Common Mode
Voltage
V_ID
V_ICM
75
2.32
mV_P-P
V
HS Differential Input Impedance
R_IN
HS Maximum Jitter Tolerance
I²C
I²C Clock Rate (on SCL)
f_I2C
I²C Clock Pulse Width (HI or LO)
I²C Clock Low to Data Out Valid
I²C Start/Stop Setup/Hold Time
I²C Data in Setup Time
I²C Data in Hold Time
I²C Data out Hold Time
80
100
120
Ω
0.50
UI_P-P
100
400
kHz
1.3
µs
0
1
µs
0.6
µs
100
ns
100
ns
100
ms
NOTES:
8. IDDIO is nominally 50µA and not included in this total as it is dominated by the loading of the parallel pins
9. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is
dependent on the PCLK frequency and is calculated as follows: 0.5 * f_IN - t_DV..
7
FN6870.1
September 23, 2010