ISL34321 Datasheet, PDF (5/13 Pages) Intersil Corporation – 16-Bit Long-Reach Video SERDES with Bi-directional Side-Channel

ISL34321
Absolute Maximum Ratings
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX,
VDD_IO to GND_IO . . . . . . . . . . . . . . . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR -0.5V to 2.5V
Between any pair of GND_P, GND_TX,
GND_IO, GND_CDR, GND_CR . . . . . . . . . . -0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS
Input Voltage . . . . . . . . . . . . . . . .-0.3V to VDD_IO+0.3V
Differential Input Voltage . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . Short Circuit Protected
LVTTL/LVCMOS Outputs . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
SERIOP/N (all VDD Connected, all GND Connected) . 8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD-78B; Class2, Level A). . . .100mA
Thermal Information
Thermal Resistance (Typical)
θ_JA
θ_JC (°C/W)
EPTQFP (Notes 6, 7) . . . . . . . . . . . 38
12
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Operating Temperature Range . . . . . . . . . . -40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
7. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V_,
VDD_TX = VDD_P = VDD_AN = 3.3V, T_A = +25°C, Ref_Res = 3.16kΩ, High-speed
AC-coupling capacitor = 27nF.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR
1.7
1.8
1.9
V
VDD_TX, VDD_P, VDD_AN, VDD_IO
3.0
3.3
3.6
V
SERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current
PCLK_IN = 45MHz
62
80
mA
Total 3.3V Supply Current
(Note 8)
40
52
mA
DESERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current
PCLK_IN = 45MHz
66
76
mA
Total 3.3V Supply Current
(Note 8)
50
63
mA
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current
RSTB = GND
10
mA
Total 3.3V Power-Down Supply Current
0.5
mA
PARALLEL INTERFACE
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
High Level Output Voltage
V_IH
V_IL
I_IN
V_OH
I_OH = -4.0mA,
VDD_IO = 3.0V
2.0
V
0.8
V
-1
±0.01
1
µA
2.6
V
Low Level Output Voltage
V_OL I_OL = 4.0mA,
VDD_IO = 3.6V
0.4
V
Output Short Circuit Current
I_OSC
35
mA
5
FN6870.1
September 23, 2010