ISL267440 Datasheet, PDF (7/17 Pages) Intersil Corporation – 10-Bit and 12-Bit, 1MSPS SAR ADCs

ISL267440, ISL267450A
Timing Specifications Limits established by characterization and are not production tested. V_DD = 3.0V to 3.6V, f_SCLK = 18MHz,
f_S = 1MSPS, V_REF = 2.0V; V_DD = 4.75V to 5.25V, f_SCLK = 18MHz, f_S = 1MSPS, V_REF = 2.5V; V_CM = V_REF unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNITS
f_SCLK
t_SCLK
t_ACQ
t_CONV
t_CSW
t_CSS
t_CDV
t_CLKDV
t_SDH
t_SW
t_DISABLE
Clock Frequency
Clock Period
Acquisition Time
Conversion Time
CS Pulse Width
CS Falling Edge to S_CLK Falling Edge Setup Time
CS Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
SCLK Pulse Width
SCLK Falling Edge to SDATA Disable Time
(Note 9)
Extrapolated back to true bus relinquish
0.01
55
10
10
10
0.4 x t_SCLK
10
18
MHz
ns
200
ns
888
ns
ns
ns
20
ns
40
ns
ns
ns
35
ns
t_QUIET Quiet Time Before Sample
60
ns
NOTE:
9. During characterization, t_DISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the
AD7440/450A loading (25pF) is calculated.
18MHz = 55.5556ns PERIOD
CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CSB
T/H TO HOLD MODE, DOUT VALID
T/H TO SAMPLE MODE
DOUT TRISTATE
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
D0
D0
D0
ISL267450A DATA OUTPUT
D0
MSB BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
DOUT
D0
D0
D0
D0
MSB BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
ISL267440 DATA OUTPUT
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
7
FN7708.0
December 5, 2011