HSP50306 Datasheet, PDF (7/8 Pages) Intersil Corporation – Digital QPSK Demodulator

HSP50306
AC Electrical Specifications 27MHz Clock Rate, V_CC = 5.0V ±5%, T_A = 0^o to 70^oC (Note 8)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
CLK Period
t_CP
36
-
ns
CLK High
t_CH
12
-
ns
CLK Low
t_CL
12
-
ns
Setup RESET to CLK
t_RS
15
-
ns
Hold Time RESET to CLK
t_RH
1
-
ns
Setup Time DIN0-5 to ADCLK
t_DS
9
15
-
ns
Hold Time DIN0-5 to ADCLK
t_DH
9
2
-
ns
CLK to DATAOUT, LOCK, AGCOUT
t_PD
-
25
ns
Output Rise, Fall Time
t_RF
10
-
8
ns
Output Rise, Fall Time (CMOS Outputs)
t_TC
10
-
12
ns
NOTES:
8. AC Testing is performed as follows: Input levels 0.0V to 3.0V. Timing reference levels = 1.5V. Output load circuit with C_L = 40pF. Output
transition measured at V_OH_1.5V and V_OL_1.5V.
9. The set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design
and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification
of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D con-
verters for use with the HSP50306.
10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design
changes.
AC Test Load Circuit
DUT
S₁
C_L
(NOTE)
SWITCH S1 OPEN FOR I_CCSB AND I_CCOP
NOTE: Test head capacitance
I_OH ± 2.5V
I_OL
EQUIVALENT CIRCUIT
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