DG441_06 Datasheet, PDF (7/14 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

DG441, DG442
Test Circuits and Waveforms (Continued)
+15V
C V+
IMPEDANCE
ANALYZER
V_S
IN_X 0V, 2.4V
f = 1MHz
V_D
C
V-
GND
-15V
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Application Information
GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE.
OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT.
+15V
FET INPUT 7 ^-15V
V_IN
OP AMP 3 4
2
6
+15V
13
V_OUT
GAIN₁
A_V = 1
GAIN₂
A_V = 10
GAIN₃
A_V = 20
GAIN₄
A_V = 100
2
1
15
16
10
9
7
8
V-
4
-15V
3
14
11
6
GND
5
R₁
90kΩ
R₂
5kΩ
R₃
4kΩ
R₄
1kΩ
V_{-----O----U----T--}
V_IN
=
R_{-----1----+-----}R_{-----2----+-----}R_{-----3----+-----}R_-----4-
R₄
=
100
with SW₄
closed
FIGURE 6. PRECISION WEIGHTED RESISTOR
PROGRAMMABLE GAIN AMPLIFIER
V_IN
+_-
IN_X
1 = SAMPLE
0 = HOLD
+15V
1/4 DG442
S_X
D_X
C_H
+_-
-15V
V_OUT
FIGURE 7. OPEN LOOP SAMPLE AND HOLD
7
FN3281.10
November 20, 2006