DG441_06 Datasheet, PDF (6/14 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

DG441, DG442
Test Circuits and Waveforms
V_O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
3V
LOGIC
INPUT
0V
50%
t_OFF
t_r < 20ns
t_f < 20ns
SWITCH
INPUT
S₁
IN₁
V+
D₁
V_O
SWITCH
INPUT
V_S
SWITCH
OUTPUT _0V
V_O
80%
t_ON
80%
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
LOGIC
INPUT
3V
GND
R_L
C_L
V-
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications. C_L includes fixture and stray
capacitance.
V_O
=
V_S
---------------^R-----^L----------------
R_L + r_DS(ON)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
ΔV_O
R_G
D₁
V_O
IN_{X OFF}
ON
OFF
(DG441)
V_G
C_L
IN_X
(DG442) ^OFF
ON
Q = ΔV_O x C_L
OFF
GND
V-
V_IN = 3V
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
+15V
C V+
SIGNAL
GENERATOR 10dBm
V_S
V_D
50Ω
+15V
C V+
SIGNAL
GENERATOR 10dBm
V_S
0V, 2.4V
IN₁
IN₂
0V, 2.4V
ANALYZER
R_L
V_D
NC
C
V-
GND
-15V
FIGURE 3. CROSSTALK TEST CIRCUIT
IN_X
0V, 2.4V
ANALYZER
R_L
V_D
C
V-
GND
-15V
FIGURE 4. OFF ISOLATION TEST CIRCUIT
6
FN3281.10
November 20, 2006