DG411883 Datasheet, PDF (7/10 Pages) Intersil Corporation – Monolithic Quad SPST CMOS Analog Switches

DG411/883, DG412/883, DG413/883
Test Circuits
V_O is the steady state output with the switch on.
Feedthrough via switch capacitance may result in spikes at
the leading and trailing edge of the output waveform.
3V
LOGIC
INPUT
0V
SWITCH
INPUT
V_S
SWITCH
OUTPUT _0V
t_R < 20ns (10% to 90% V_IN)
t_F < 20ns (90% to 10% V_IN)
V_G
50%
t_OFF
V_O
0.9 V_O
0.9 V_O
t_ON
NOTE: Logic input waveform is inverted for switches that have
the opposite logic sense.
V+
R_G
D₁
V-
V_IN = 3V
GND
FIGURE 2A.
V_O
C_L
∆V_O
0V
FIGURE 1A.
IN_X
OFF
ON
OFF
SWITCH
INPUT
S₁
IN₁
+5V
V_L
+15V
V+
D₁
SWITCH
OUTPUT
V_O
LOGIC
INPUT
GND
V-
-15V
R_L
C_L
Repeat test for all IN and S.
For load conditions, see Specifications C_L (includes fixture and
stray capacitance)
VO = VS _R----_L----+-----_R--^R--_D-^L--_S----₍--_O----_N---₎
OFF
IN_X
ON
Q = ∆V_O x C_L
OFF
IN_X dependent on switch configuration input polarity determined by
sense of switch.
FIGURE 2B.
FIGURE 2. CHARGE INJECTION
FIGURE 1B.
FIGURE 1. SWITCHING TIME
Spec Number 512043
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