DG408_14 Datasheet, PDF (7/17 Pages) Intersil Corporation – Single 8-Channel/Differential 4-Channel, CMOS Analog Multiple

DG408, DG409
Test Circuits and Waveforms (Continued)
+2.4V
LOGIC
INPUT
50Ω
+15V
V+
EN ALL S AND D_A
A_{0 DG408}
A₁ ^DG409
A_{2 GND V-} D, D_B
+5V (V_S)
300Ω
SWITCH
OUTPUT
V_O
35pF
-15V
LOGIC ^3V
INPUT
0V
V_S
SWITCH
OUTPUT
V_O
0V
80%
80%
t_OPEN
t_r < 20ns
t_f < 20ns
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V
V_GEN
R_GEN
CHANNEL
SELECT
LOGIC INPUT
S_X
A₀
A₁
A₂
EN GND
V+
D
V-
-15V
V_O
C_L
10nF
3V
LOGIC
INPUT _0V
SWITCH
OUTPUT
ON
OFF
∆V_O
∆V_O IS THE MEASURED VOLTAGE DUE
TO CHARGE TRANSFER ERROR, Q
Q = C_L x ∆V_O
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. CHARGE INJECTION
0V +15V
V_IN
S_X EN V+
|
|
V_O
S₈
D
SIGNAL
GENERATOR
A₂
1kΩ
A₁
A₀
V-
GND
-15V
ANALYZER
OFF ISOLATION = 20 Log ^{V-----O-----U-----T--}
VIN
FIGURE 5. OFF ISOLATION
7
5V +15V
1kΩ
V_IN
SIGNAL
GENERATOR
S_{1 EN V+}
S_X
|
|
V_O
S₈
D
A₂
1kΩ
A₁
A₀
V-
ANALYZER
GND
-15V
CROSSTALK = 20 Log ^{V-----O-----U-----T--}
VIN
FIGURE 6. CROSSTALK
FN3283.8
June 13, 2006