DG408_14 Datasheet, PDF (6/17 Pages) Intersil Corporation – Single 8-Channel/Differential 4-Channel, CMOS Analog Multiple

DG408, DG409
Test Circuits and Waveforms
+2.4V
+15V
LOGIC
INPUT
50Ω
EN
V+ _S1
A₀
S₂ - S₇
A₁ ^DG408 S₈
A_{2 GND V-} D
±10V
10V
300Ω
-15V
SWITCH
OUTPUT
V_O
35pF
+2.4V
LOGIC
INPUT
50Ω
+15V
EN
V+S_1B
S_1A - S_4A, D_A
A₀ ^DG409 S_4B
A_{1 GND V-} D_B
±10V
10V
300Ω
-15V
SWITCH
OUTPUT
V_O
35pF
FIGURE 1A. DG408 TEST CIRCUIT
FIGURE 1B. DG409 TEST CIRCUIT
LOGIC ^3V
INPUT _0V
V_S1
SWITCH
OUTPUT _0V
V_O
V_S8
S₁ ON
t_TRANS
50%
50%
0.8 V_S8
S₈ ON
t_r < 20ns
t_f < 20ns
0.8 V_S1
t_TRANS
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. TRANSITION TIME
+15V
+15V
LOGIC
INPUT V_IN
50Ω
A₀
V+
DG408
S₁
-5V
A₁
S₂ - S₈
A₂
EN _{GND V-} ^D
300Ω
-15V
SWITCH
OUTPUT
V_O
35pF
FIGURE 2A. DG408 TEST CIRCUIT
LOGIC
INPUT V_IN
50Ω
A_{0 DG409V+S1B}
-5V
A₁
S_1A - S_4A
S_{2B -} S_4B, D_A
EN _{GND V-} ^DB
300Ω
-15V
SWITCH
OUTPUT
V_o
35pF
FIGURE 2B. DG409 TEST CIRCUIT
3V
LOGIC
INPUT
V_IN
0V
0V
SWITCH
OUTPUT
V_O
V_O
50%
50%
t_ON(EN)
0.9 V_O
t_r < 20ns
t_f < 20ns
t_OFF(EN)
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE SWITCHING TIMES
6
FN3283.8
June 13, 2006