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DG401883 Datasheet, PDF (7/12 Pages) Intersil Corporation – Monolithic CMOS Analog Switches
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Test Circuits
DG401/883, DG403/883, DG405/883
3V
LOGIC
INPUT
0V
50%
tR < 20ns
tF < 20ns
tOFF
SWITCH
INPUT
VS
SWITCH
OUTPUT 0V
SWITCH
INPUT
(NOTE 2)
VS
VO
0.9 VO
tON
0.9 VO
0.9 VO
NOTES:
1. Logic input waveform is inverted for switches that have the
opposite logic sense.
2. VS = 10V for tON, VS = -10V for tOFF.
FIGURE 1A.
SWITCH
INPUT
S1
IN1
LOGIC
INPUT
5V
VL
+15V
V+
RL = 300Ω
CL = 35pF
D1
VO
GND
RL
CL
V-
0V
-15V
Repeat test for IN2 and S2
For load conditions, see Specifications. CL (includes fixture
and stray capacitance)
VO
=
VS
---------------R----L----------------
RL + rDS (ON)
FIGURE 1B.
FIGURE 1. SWITCHING TIME
3V
LOGIC
INPUT
0V
VS1
SWITCH
OUTPUT
0V
VS2
VO2
SWITCH
OUTPUT
0V
50%
VO1
0.9 VO
tD
0.9 VO
tD
VS1 = 10V
VS2 = 10V
IN1
LOGIC
INPUT
5V
VL
+15V
V+
RL = 300Ω
CL = 35pF
D1
VO1
D2 VO2
RL1
CL1
GND
RL2
CL2
V-
0V
-15V
CL (includes fixture and stray capacitance)
FIGURE 2A.
FIGURE 2. BREAK-BEFORE-MAKE
FIGURE 2B.
Burn-In Circuit
DG401/883, DG403/883, DG405/883
R1
1 D1
S1 16
R2
2
A1 15
3 D3
V- 14
4 S3
VR 13
5 S4
VL 12
R3
6 D4
V+ 11
7
A2 10
R4
8 D2
S2 9
C1
C2
C3
VA
V-
D2
VL
V+
D3
Spec Number 512046
4-7
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