CDP1878C Datasheet, PDF (7/13 Pages) Intersil Corporation – CMOS Dual Counter-Timer

CDP1878C
MODE
CONTROL REGISTER
GATE CONTROL
2
Timeout Strobe
Selectable High or Low
X X X X X 0 1 0 _{Level Enables Operation}
BUS 7
BUS 0
Mode 2
Operation of this mode is the same as mode 1, except the
outputs will change for one clock period only and then return
to the condition of TXO high and TXO low, and the counter is
reloaded
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
3
2
1
0
3
3
2
1
3
2
1
0
3
3
2
1
0
SEE NOTE
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 2. TIMEOUT STROBE (MODE 2) TIMING WAVEFORMS
NOTE: Write to control register with mode selects = 0
MODE
CONTROL REGISTER
3 ^{Gate Controlled One-Shot}
0 XXXX011
BUS 7
BUS 0
GATE CONTROL
Selectable Positive or
Negative Going Edge
Initiates Operation
Mode 3
After the jam register is loaded with the required value, the
gate edge will initiate this mode. TXO will be set high, and
TXO will be set low. The clock will decrement the counter.
When zero is reached, TXO will go low and TXO will be high,
and the interrupt output will be set low. The counter is retrig-
gerable: While the counter is decrementing, a gate edge or
write to the control register with the jam-enable bit high, will
load the counter with the jam register value and restart the
one-shot operation.
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
3
2
1
0
3
3
2
3
2
1
0
3
3
2
1
TXO
INT
LOAD COUNT = 3
FIGURE 3. GATE CONTROLLED ONE-SHOT (MODE 3) TIMING WAVEFORMS
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