CDP1878C Datasheet, PDF(1/13 Page) Intersil Corporation

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CDP1878C Datasheet, PDF (1/13 Pages) Intersil Corporation – CMOS Dual Counter-Timer

CDP1878C

March 1997

CMOS Dual Counter-Timer

Features

â¢ Compatible with General Purpose and CDP1800

Series Microprocessor Systems

â¢ Two 16-Bit Down Counters and Two 8-Bit Control

Registers

â¢ 5 Modes Including a Versatile Variable-Duty Cycle

Mode

â¢ Programmable Gate-Level Select

â¢ Two-Complemented Output Pins for Each Counter-

Timer

â¢ Software-Controlled Interrupt Output

â¢ Addressable in Memory Space or CDP1800-Series I/O

Space

Ordering Information

PART

NUMBER

CDP1878CE

CDP1878CD

TEMP. RANGE PACKAGE

-40oC to +85oC PDIP

-40oC to +85oC SBDIP

PKG. NO.

E28.6

N28.6

Description

The CDP1878C is a dual counter-timer consisting of two 16-

bit programmable down counters that are independently

controlled by separate control registers. The value in the reg-

isters determine the mode of operation and control func-

tions. Counters and registers are directly addressable in

memory space by any general industry type microproces-

sors, in addition to input/output mapping with the CDP1800

series microprocessors.

Each counter-timer can be conï¬gured in ï¬ve modes with the

additional ï¬exibility of gate-level control. The control regis-

ters in addition to mode formatting, allow software start and

stop, interrupt enable, and an optional read control that

allows a stable readout from the counters. Each counter-

timer has software control of a common interrupt output with

an interrupt status register indicating which counter-timer

has timed out.

In addition to the interrupt output, true and complemented

outputs are provided for each counter-timer for control of

peripheral devices.

This type is supplied in 28-lead dual-in-line ceramic pack-

ages (D sufï¬x), and 28-lead dual-in-line plastic packages (E

sufï¬x).

Pinout

CDP1878C

(DIP)

TOP VIEW

INT 1

TAO 2

TAO 3

TAG 4

TACL 5

RD 6

IO/MEM 7

TPB/WR 8

TPA 9

CS 10

A0 11

A1 12

A2 13

VSS 14

28 VDD

27 DB7

26 DB6

25 DB5

24 DB4

23 DB3

22 DB2

21 DB1

20 DB0

19 TBO

18 TBO

17 TBG

16 TBCL

15 RESET

TABLE 1. MODE DESCRIPTION

MODE

FUNCTION

APPLICATION

1 Timeout

Outputs change when clock Event counter

decrements counter to â0â

2 Timeout

Strobe

One clockwide output pulse

when clock decrements

counter to â0â

Trigger pulse

3 Gate-Con-

trolled One

Shot

Outputs change when clock

decrements counter to â0â.

Retriggerable

Time-delay

generation

4 Rate Generator Repetitive clockwide output Time-base

pulse

generator

5 Variable-Duty Repetitive output with

Cycle

programmed duty cycle

Motor control

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-91

File Number 1341.2

▷