CD4099BMS Datasheet, PDF (7/10 Pages) Intersil Corporation – CMOS 8-Bit Addressable Latch

CD4099BMS
70%
A0
30%
70%
A1
30%
A2
WD
70%
tW
MODE SELECTION
WD R
ADDRESSED
LATCH
UNADDRESSED
LATCH
0 0 Follows Data
Holds Previous
State
0 1 Follows Data
Reset to “0”
(Active High 8-Channel Demultiplexer)
10
Holds Previous State
1 1 Reset to “0”
Reset to “0”
WD = Write Disable R = Reset
FIGURE 2. DEFINITION OF WRITE DISABLE ON TIME
A0, A1, A2
WRITE DISABLE
DATA
RESET
Q0
Q7
Q7
tW
8
4
tW
tH
7
tS
6
tP
9
tP
tP
1
tP
FIGURE 3. MASTER TIMING DIAGRAM
tW
5
tP
2
tP
3
tP
A0
A1
A2
A3
DATA IN
5 _A0
6 _A1
7
A2
4
WD
3
DATA
R
Q0 ⁹ DO 1
Q1 ¹⁰ DO 2
Q2 ¹¹ DO 3
Q3 ¹² DO 4
Q4 ¹³ DO 5
Q5 ¹⁴ DO 6
Q6 ¹⁵ DO 7
Q7 ¹ DO 8
2
VDD
5
6
7
4
*
3
*1/6 CD4069
A0
A1
A2
WD
DATA
R
Q0 ⁹ DO 9
Q1 ¹⁰ DO 10
Q2 ¹¹ DO 11
Q3 ¹² DO 12
Q4 ¹³ DO 13
Q5 ¹⁴ DO 14
Q6 ¹⁵ DO 15
Q7 ¹ DO 16
2
VDD
FIGURE 4. 1 OF 16 DECODER/DEMULTIPLEXER
DATA
A0
A1
A2
A3
CD4099BMS
Q0
D
Q1
WD
R
CD4099BMS
D
Y
1/4 CD4016 ^IN/OUT
0
1
2
S0
S1
S5
3
S2
0
1
X
IN/OUT
2
WD
WD
Q15
3
R
WD
FIGURE 5. MULTIPLE SELECTION DECODING - 4 x 4 CROSSPOINT SWITCH
7-500