CD4099BMS Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS 8-Bit Addressable Latch

Specifications CD4099BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
1, 9-15
GROUND
2-8
VDD
16
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
1, 9-15
8
2-7, 16
Note 1
Dynamic Burn-
-
In Note 1
5-8
16
1, 9-15
2, 4
3
Irradiation
1, 9-15
8
2-7, 16
Note 2
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
5*
A0
6*
A1
7*
A2
3*
DATA
4*
WRITE DISABLE
2*
RESET
R
ADDRESS
WD
DATA
A0
A0
A1
A1
A2
A2
D
WD
R
p
n
p
n
A0
A1
A2
A0
A1
A2
A0
A1
A2
A0
A1
A2
A0
A1
A2
A0
A1
A2
A0
A1
A2
A0
A1
A2
Q
D
WD
LATCH
0
9
Q0
R
D
WD
LATCH
1
10
Q1
R
D
WD
LATCH
2
11
Q2
R
D
WD
LATCH
3
12
Q3
R
D
WD
LATCH
4
13
Q4
R
D
WD
LATCH
5
14
Q5
R
D
WD
LATCH
6
15
Q6
R
D
WD
LATCH
7
1
Q7
R
VDD
VSS = 8
VDD = 16
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
7-499