CD4048BMS Datasheet, PDF (7/11 Pages) Intersil Corporation – CMOS Multifunction Expandable 8 Input Gate

Logic Diagrams (Continued)
11
12
13
14
15
3
4
5
6
AND
CD4048BMS
NOR
Ka - Kb - Kc
0-0-0
OR
NAND
1-0-1
AND/OR
1-0-0
AND/NOR
0-0-1
OR/NAND
1-1-1
OR/AND
1-1-0
0-1-1
0-1-0
FIGURE 3. ACTUAL CIRCUIT LOGIC CONFIGURATIONS
Applications of Expand Input
VDD
J (OUTPUT) ₁
VDD
Kd ₂
H3
16
X1
15
X2
X3
14 A
X4
G4
13 B 1/2 CD4002A
F5
12 C
VDD
E6
Kb ₇
11 D
10 Ka
VSS 8
9 Kc
VSS
12 - INPUT OR/AND GATE
J = (A+B+C+D) ^. (E+F+G+H) ^. (X1+X2+X3+X4)
FIGURE 4. 12 INPUT OR/AND GATE
OR FUNCTION
VDD J(OUTPUT)
VDD
OUTPUT
1
VDD ^{Kd 2}
H1 3
16
15
VSS
14 A1
1
VDD ^Kd 2
H2 3
16
15 ^EXP
14 A2
G1 4
13 B1
G2 4
13 B2
F1 5
12 C1
F2 5
12 C2
E1 6
Kb ₇
8
VSS
11 D1
10 ^Ka
9 ^Kc
VSS
VDD
E2 6
Kb ₇
8
VSS
11 D2
10 ^Ka
9 ^Kc
16 - INPUT NOR GATE
J = A1 +B1 +C1 +D1 +E1 +F1 +G1 +H1 +A2 +B2 +C2 +D2 +E2 +F2 +G2 +H2
VSS
FIGURE 5. 16 INPUT NOR GATE
IMPLEMETATION OF EXPAND INPUT FOR 9 OR MORE INPUTS
OUTPUT FUNCTION FUNCTION NEEDED AT EXPAND INPUT OUTPUT BOOLEAN EXPRESSION
NOR
OR
J=(A+B+C+D+E+F+G+H)+(EXP)
OR
OR
J=(A+B+C+D+E+F+G+H)+(EXP)
AND
NAND
J=(ABCDEFGH)•(EXP)
NAND
NAND
J=(ABCDEFGH)•(EXP)
OR/AND
NOR
J=(A+B+C+D)•(E+F+G+H)•(EXP)
OR/NAND
NOR
J=(A+B+C+D)•(E+F+G+H)•(EXP)
AND/NOR
AND
J=(ABCD)+(EFGH)+(EXP)
AND/OR
AND
J=(ABCD)+(EFGH)+(EXP)
NOTES: 1. (EXP) designates the EXPAND function (i.e., X1 + X2 + . . .XN).
2. Refer to FUNCTION TRUTH TABLE for connection of unused inputs.
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