CD4046BMS Datasheet, PDF (7/11 Pages) Intersil Corporation – CMOS Micropower Phase Locked Loop

CD4046BMS
Design Information
This information is a guide for approximating the values of external components for the CD4046BMS in a Phase-Locked-
Loop system. The selected external components must be within the following ranges:
5kΩ ≤ R1, R2, RS ≤ 1MΩ
C1 ≥ 100pF at VDD ≥ 5V
C1 ≥ 50pF at VDD ≥ 10V
CHARACTERISTICS
PHASE
COMPARATOR USED
DESIGN INFORMATION
VCO Frequency
1
VCO Without Offset R2 = ∞
VCO With Offset
f_MAX
f_O
2f_L
f_MIN
VDD/2 VDD
VCO INPUT VOLTAGE
f_O
f_MAX
2f_L
f_MIN
VDD/2 VDD
VCO INPUT VOLTAGE
For Number Signal Input
Frequency Lock Range, 2fL
Frequency Capture Range, 2fC
Loop Filter Component Selection
2
Same as for Number 1
1
VCO will adjust to center frequency, fo
2
VCO will adjust to lowest operating frequency, fmin
1, 2
2fL = full VCO frequency range
1, 2
2fL = fmax - fmin
1
IN R3
OUT
(1), (2)
τI = R3C2 C2
√ 2fC ≈ 1
π
2πfL
τ1
IN R3
OUT
R4
For 2 fC, see Ref. (2)
C2
Phase Angle Between Signal and
Comparator
2
fC = fL
1
90^o at center frequency (fo) approximating 0^o and 180^o at ends of lock
range (2fL)
2
Always 0^o in lock
Locks On Harmonic of Center
Frequency
1
Yes
2
No
Signal Input Noise Rejection
1
High
2
Low
For further information, see
(1) F. Gardner, “Phase-Lock Techniques” John Wiley and Sons, New York 1966
(2) G. S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965
7-892