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CD40192BMS Datasheet, PDF (7/12 Pages) Intersil Corporation – CMOS Presettable Up/Down Counters (Dual Clock With Reset)
Logic Diagrams
*RESET
14
*PE
11
*J1
15
CD40192BMS, CD40193BMS
CONTROL LOGIC 1
S1
R1
S2
S3
S4
**
R2 **
R3 **
R4
1
10
9
*J2
*J3
*J4
**SAME AS CONTROL LOGIC 1
*CLOCK UP
5
4
*CLOCK DOWN
S1
S
Q1
CL
Q1
R
R1
S2
S
Q2
CL
Q2
R
R2
VDD
S3
S
Q3
CL
Q3
R
R3
CARRY
12
S4
S
Q4
CL
Q4
R
R4
13
BORROW
3
2
Q1
Q2
VSS
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
6
7
Q3
Q4
FIGURE 1. CD40192BMS LOGIC DIAGRAM (BCD)
7-1425