CA3318 Datasheet, PDF (7/12 Pages) Intersil Corporation – CMOS Video Speed, 8-Bit, Flash A/D Converter

CA3318
Typical Performance Curves (Continued)
8.0
7.6
7.2
f_S = 15MHz
6.8
6.4
6.0
5.6
5.2
4.8
4.4
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
f_I (MHz)
FIGURE 10. ENOB vs INPUT FREQUENCY
Pin Descriptions
PIN
NAME
DESCRIPTION
1
B1
Bit 1 (LSB)
Output Data Bits
2
B2
Bit 2
(High = True)
3
B3
Bit 3
4
B4
Bit 4
5
B5
Bit 5
6
B6
Bit 6
7
B7
Bit 7
8
B8
Bit 8 (MSB)
9
OF
Overflow
10
1_{/4 R}
Reference Ladder ¹/₄ Point
11
V_SS
Digital Ground
12
V_DD
Digital Power Supply, +5V
13
CE2
Three-State Output Enable Input,
Active Low, See Truth Table.
14
CE1
Three-State Output Enable Input
Active High. See Truth Table.
15
V_REF- Reference Voltage Negative Input
16
V_IN
Analog Signal Input
17
V_AA-
Analog Ground
18
CLK
Clock Input
19
PHASE Sample clock phase control input.
When PHASE is low, “Sample
Unknown” occurs when the clock is
low and “Auto Balance” occurs when
the clock is high (see text).
20
1_{/2 R}
Reference Ladder Midpoint
21
V_IN
Analog Signal Input
22
V_REF+ Reference Voltage Positive Input
23
3_{/4 R}
Reference Ladder ³/₄ Point
24
V_AA+
Analog Power Supply, +5V
CHIP ENABLE TRUTH TABLE
CE1
CE2
B1 - B8
0
1
Valid
1
1
Three-State
X
0
Three-State
X = Don’t Care
OF
Valid
Valid
Three-State
Theory of Operation
A sequential parallel technique is used by the CA3318
converter to obtain its high speed operation. The sequence
consists of the “Auto-Balance” phase, φ1, and the “Sample
Unknown” phase, φ2. (Refer to the circuit diagram.) Each
conversion takes one clock cycle (see Note). With the phase
control (pin 19) high, the “Auto-Balance” (φ1) occurs during
the high period of the clock cycle, and the “Sample Unknown”
(φ2) occurs during the low period of the clock cycle.
NOTE: The device requires only a single phase clock The terminology
of φ1 and φ2 refers to the high and low periods of the same clock.
During the “Auto-Balance” phase, a transmission switch is
used to connect each of the first set of 256 commutating
capacitors to their associated ladder reference tap. Those
tap voltages will be as follows:
V_TAP (N) = [(N/256) V_REF] - (1/512) V_REF]
= [(2N - 1)/512] V_REF,
Where:
V_TAP (n) = reference ladder tap voltage at point n,
V_REF = voltage across V_REF- to V_REF+,
N
= tap number (1 through 256).
The other side of these capacitors are connected to single-
stage amplifiers whose outputs are shorted to their inputs by
switches. This balances the amplifiers at their intrinsic trip
points, which is approximately (V_AA+ - V_AA-)/2. The first set
of capacitors now charges to their associated tap voltages.
4-15