CA3318 Datasheet, PDF (4/12 Pages) Intersil Corporation – CMOS Video Speed, 8-Bit, Flash A/D Converter

CA3318
Electrical Specifications At 25^oC, V_AA+ = V_DD = 5V, V_REF+ = 6.4V, V_REF - = V_AA- = V_SS, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Low Level Input Voltage, V_OL
CE1, CE2
Phase, CLK
High Level Input Voltage, V_IN
CE1, CE2
Phase, CLK
Input Leakage Current, I_I (Except CLK Input)
Input Capacitance, C_I
DIGITAL OUTPUTS
Note 4
Note 4
Note 4
Note 4
Note 3
-
-
0.2V_DD
V
-
-
0.2V_AA
V
0.7V_DD
-
-
V
0.7V_AA
-
-
V
-
±0.2
±5
µA
-
3
-
pF
Output Low (Sink) Current
Output High (Source) Current
Three-State Output Off-State Leakage Current, I_OZ
Output Capacitance, C_O
TIMING CHARACTERISTICS
V_O = 0.4V
V_O = 4.5V
4
10
-
mA
-4
-6
-
mA
-
±0.2
±5
µA
-
4
-
pF
Auto Balance Time (φ1)
33
-
∞
ns
Sample Time (φ2)
Note 4
25
-
500
ns
Aperture Delay
-
15
-
ns
Aperture Jitter
-
100
-
ps
Data Valid Time, t_D
Data Hold Time, t_H
Output Enable Time, t_EN
Output Disable Time, t_DIS
POWER SUPPLY CHARACTERISTICS
Note 4
Note 4
-
50
65
ns
25
40
-
ns
-
18
-
ns
-
18
-
ns
Device Current (I_DD + I_A) (Excludes I_REF)
Continuous Conversion (Note 4)
-
Auto Balance (φ1)
-
30
60
mA
30
60
mA
NOTES:
1. A full scale sine wave input of greater than f_CLOCK/2 or the specified input bandwidth (whichever is less) may cause an erroneous code.
The -3dB bandwidth for frequency response purposes is greater than 30MHz.
2. V_IN (Full Scale) or V_REF+ should not exceed V_AA+ + 1.5V for accuracy.
3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1V_P-P minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
Timing Waveforms
COMPARATOR DATA IS LATCHED
CLOCK (PIN 18)
IF PHASE (PIN 19)
IS LOW
φ2
φ1
DECODED DATA IS SHIFTED
TO OUTPUT REGISTERS
φ2
φ1
φ2
CLOCK IF
PHASE IS HIGH
SAMPLE
N
AUTO
BALANCE
DATA
N-2
SAMPLE
N+1
AUTO
BALANCE
t_D
t_H
DATA
N-1
SAMPLE
N+2
DATA
N
FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM
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