KAD5612P Datasheet, PDF (6/27 Pages) List of Unclassifed Manufacturers – Dual 12-Bit, 250/210/170/125MSPS A/D Converter

KAD5612P
Digital Specifications
PARAMETER
INPUTS
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Capacitance
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
Timing Diagrams
Sample N
INP
SYMBOL
CONDITIONS
I_IH
V_IN = 1.8V
I_IL
V_IN = 0V
I_IH
I_IL
C_DI
V_T
V_OS
t_R
t_F
3mA Mode
3mA Mode
V_OH
V_OL
t_R
t_F
I_OH = -500µA
I_OL = 1mA
MIN
TYP
MAX
0
1
10
-25
-12
-5
15
25
40
-40
25
-15
3
620
950
965
980
500
500
OVDD - 0.3 OVDD - 0.1
0.1
0.3
1.8
1.4
UNITS
µA
µA
µA
µA
pF
mV_P-P
mV
ps
ps
V
V
ns
ns
Sample N
INP
IN N
tA
C LKN
CL KP
t_{C PD}
C LKOUTN
C LKOUTP
D[11:0 ]P
A Data
D[ 11:0]N
N-L
tDC
t _PD
B Data
N -L
Latency = L Cycles
A Data
N-L+1
B D ata
N-L+ 1
A Data
N-L+2
B Data
N-L+ 2
AD ata
N
FIGURE 1. LVDS TIMING DIAGRAM—DDR
INN
tA
CLKN
C LK P
t_{C PD}
Latency = L Cycles
C LK OUT
D[ 11:0]
A Data
N-L
t _DC
tPD
BD ata
N-L
A Data
N-L+1
B Data
N-L +1
A Data
N-L+2
BD ata
N- L+2
A Data
N
FIGURE 2. CMOS TIMING DIAGRAM—DDR
6
FN6803.0
December 5, 2008