KAD5612P Datasheet, PDF (16/27 Pages) List of Unclassifed Manufacturers – Dual 12-Bit, 250/210/170/125MSPS A/D Converter

KAD5612P
A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52µs to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t_J) and SNR is shown in Equation 1 and
is illustrated in Figure 31.
SNR
=
20
log₁₀
⎛
⎝
2^----π^----f^-1-_I^--_N^----t^--_J^{-⎠⎞}
(EQ. 1)
10 0
95
90
85
80
75
70
65
60
55
50
1
tj=0.1p s
tj=1 ps
tj=1 0 0p s
tj=10p s
10
10 0
Input Frequency - MHz
1 4 Bits
1 2 Bits
10 Bits
1 0 00
FIGURE 31. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The nominal value of the voltage
reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. In either case, the data
is presented in double data rate (DDR) format with the A and
B channel data available on alternating clock edges. When
CLKOUT is low channel A data is output, while on the high
phase channel B data is presented. Figures 1 and 2 show
the timing relationships for LVDS and CMOS modes,
respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 18.
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over range condition. The OR bit is updated at the sample
rate.
Power Dissipation
The power dissipated by the KAD5612P is primarily
dependent on the sample rate and the output modes: LVDS
vs. CMOS and DDR vs. SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required. Two
power saving modes are available: Nap, and Sleep. Nap
mode reduces power dissipation to less than 134mW and
recovers to normal operation in approximately 1µs. Sleep
mode reduces power dissipation to less than 14mW but
requires 1ms to recover.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep. Recovery time from Nap mode will increase if the
clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
16
FN6803.0
December 5, 2008