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| ISL6740A Datasheet, PDF (6/15 Pages) Intersil Corporation – Flexible Double-Ended Voltage-Mode PWM Controller with Voltage Feed Forward | |||
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ISL6740A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. 9V < VDD < 20 V, RTD = 51.1kâ¦, RTC = 10kâ¦, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical
values are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Minimum Duty Cycle
Maximum Duty Cycle
VERROR < CT Valley Voltage
VERROR > 4.75V, VUV/FF = 2.5V (Note 6)
RTD = 5.11kâ¦, RTC = 25.5kâ¦, CT = 220pF
-
-
0
%
-
83
-
%
-
99
-
%
VERROR to PWM Comparator Input Gain
CT to PWM Comparator Input Gain
SS to PWM Comparator Input Gain
(Note 4)
(Note 4)
(Note 4)
-
0.4
-
V/V
-
0.4
-
V/V
-
0.5
-
V/V
OSCILLATOR
Frequency Accuracy
Frequency Variation with VDD
TA = 25°C (Note 7)
333
351
369
kHz
TA = 105°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
-
0.1
0.4
%
(Note 4)
TA = 25°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
TA = -40°C, |(F20V - F9V)/F9V|, UV/FF = 2.00V
(Note 4)
-
0.1
0.3
-
0.2
0.7
Frequency Variation with VUV/FF
Temperature Stability
Charge Current Gain
TA = 25°C, |(F4.25V - F2.00V)/F2.00V|
VDD = 9V
VDD = 20V
VUV/FF = 2.0V, VDD = 9V (Note 4)
%
-
1.2
3
%
-
1.2
3
%
-
0.5
1.5
%
1.88
2.0
2.12 µA/µA
Discharge Current Gain
45
55
65 µA/µA
CT Valley Voltage
CT Peak Voltage
CT Peak Voltage
SYNCHRONIZATION
Static operation
Static operation
VUV/FF = 2.00V
VUV/FF = 4.25V
Static operation
VUV/FF = 2.00V
VUV/FF = 4.25V
0.75 0.80 0.85
V
2.30 2.40 2.50
V
4.10 4.20 4.30
V
2.30 2.40 2.50
V
4.10 4.20 4.30
V
Input High Threshold (VIH), Minimum
4.0
-
-
V
Input Low Threshold (VIL), Maximum
-
-
0.8
V
Input Impedance
-
4.5
-
kâ¦
Input Frequency Range
(Note 4)
0.6x
-
Free
Hz
Free
Running
Running
Input Pulse Width
(Note 4)
100
-
-
ns
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
SYNC Output Current
ILOAD = -1mA
ILOAD = 10µA
VOH > 2.0V (Note 4)
-
4.5
-
V
-
-
100
mV
-10
-
-
mA
SYNC Output Pulse Duration (minimum)
(Notes 4, 5)
250
-
400
ns
SYNC Advance
SYNC rising edge to GATE falling edge,
COUTA/B = CSYNC = 100pF
(Note 4)
-
5
-
ns
6
FN9195.0
February 7, 2005
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