ISL6740A Datasheet, PDF (12/15 Pages) Intersil Corporation – Flexible Double-Ended Voltage-Mode PWM Controller with Voltage Feed Forward

ISL6740A
stops at least 50µs prior to the soft-start voltage decreasing
to 4.25V, the soft-start charging currents revert to normal
operation and the soft-start voltage is allowed to recover.
4.5 V
SS
0.6 V OC
CS
OUTA
OUTB
FIGURE 7. PULSE-BY-PULSE OC BEHAVIOR DURING SS
Figure 7 shows the overcurrent behavior during SS.
Although an overcurrent condition exists, a shutdown is not
allowed prior to completion of the SS cycle. Only peak
current limit operates during the soft-start cycle. If the
overcurrent condition were to continue beyond the soft-start
cycle, a delayed overcurrent shutdown would occur as
shown in Figure 8.
SS
0.6 V OC
CS
OUTA
4.5 V
4.25 V
0.27 V
OUTB
FIGURE 8. OC SHUTDOWN BEHAVIOR
Figure 8 portrays the typical delayed overcurrent shutdown
behavior. Once SS has discharged to 4.25V, the outputs are
disabled and remain that way until SS has discharged to
0.27V, and then a new SS cycle begins.
SS
0.6 V OC
4.25 V
CS
OUTA
4.5 V
OC
50 µS
OUTB
FIGURE 9. OC RECOVERY PRIOR TO SHUTDOWN
12
If the overcurrent condition is removed prior to a shutdown, a
recovery can occur as indicated in Figure 9. When the load
decreases below the overcurrent threshold and an additional
50µs elapses without the SS dropping below 4.25V, the
overcurrent circuitry resets and the soft-start voltage
recovers.
The duration of the OC shutdown period can be increased
by adding a resistor between VREF and SS. The value of
the resistor must be large enough so that the minimum
specified SS discharge current is not exceeded. Using a
422kΩ resistor, for example, will result in a small current
being injected into SS, effectively reducing the discharge
current. This will nearly double the OFF time. The external
pull-up resistor will also decrease the SS duration, so its
effect should be considered when selecting the value of the
SS capacitor.
1
16
2
VREF 15
3
14
4
13
5
ISL6740A
12
R
6
11
7
10
8
SS 9
C_SS
FIGURE 10. MODIFYING OC SHUTDOWN TIMING
Latching OC shutdown is also possible by using a lower
valued resistor between VREF and SS. If the SS node is not
allowed to discharge below the SS reset threshold, the IC
will not recover from an overcurrent fault. The value of the
resistor must be low enough so that the maximum specified
discharge current is not sufficient to pull SS below 0.33V. A
200kΩ resistor, for example, prevents SS from discharging
below ~0.4V. Again, the external pull-up resistor will
decrease the SS duration, so its effect should be considered
when selecting the value of the SS capacitor
Short Circuit Operation
If the output current increases beyond the overcurrent
threshold, peak current limit will reduce the duty cycle. As
the load current continues to increase, the duty cycle
continues to decrease. A short circuit event is defined as the
simultaneous occurrence of current limit and a reduced duty
cycle.
The degree of reduced duty cycle that defines a short circuit
condition is user adjustable using the SCSET input. A
resistor divider between R_TD, R_TC, or V_REF and GND to
RCSET sets a threshold that is compared to the voltage on
the timing capacitor, C_T. The resistor divider voltage divided
FN9195.0
February 7, 2005