ISL6609_06 Datasheet, PDF (6/11 Pages) Intersil Corporation – Synchronous Rectified MOSFET Driver

Timing Diagram
ISL6609, ISL6609A
PWM
UGATE
LGATE
t_PDLL
t_PDHU
t_PDLU
t_RU
1V
2.5V
1V
t_RL
t_PDHL
t_TSSHD
t_RU
t_FU
t_PTS
t_TSSHD
t_FL
t_PTS
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6609/09A MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t_PDLL], the lower gate begins to fall. Typical fall times
[t_FL] are provided in the Electrical Specifications. Adaptive
shoot-through circuitry monitors the LGATE voltage and
turns on the upper gate following a short delay time [t_PDHU]
after the LGATE voltage drops below ~1V. The upper gate
drive then begins to rise [t_RU] and the upper MOSFET
turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLU] is encountered before the upper
gate begins to fall [t_FU]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time, t_PDHL, after the upper
MOSFET’s gate voltage drops below 1V. The lower gate then
rises [t_RL], turning on the lower MOSFET. These methods
prevent both the lower and upper MOSFETs from conducting
simultaneously (shoot-through), while adapting the dead
time to the gate charge characteristics of the MOSFETs
being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower
MOSFET conducts for a longer time during a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
absorb the current injected into the lower gate through the
drain-to-gate capacitor of the lower MOSFET and help
prevent shoot through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Three-State PWM Input
A unique feature of the ISL6609/09A is the adaptable three-
state PWM input. Once the PWM signal enters the shutdown
window, either MOSFET previously conducting is turned off.
If the PWM signal remains within the shutdown window for
longer than the gate turn-off propagation delay of the
previously conducting MOSFET, the output drivers are
disabled and both MOSFET gates are pulled and held low.
The shutdown state is removed when the PWM signal
moves outside the shutdown window. The PWM rising and
falling thresholds outlined in the Electrical Specifications
determine when the lower and upper gates are enabled.
During normal operation in a typical application, the PWM
rise and fall times through the shutdown window should not
exceed either output’s turn-off propagation delay plus the
MOSFET gate discharge time to ~1V. Abnormally long PWM
signal transition times through the shutdown window will
simply introduce additional dead time between turn off and
turn on of the synchronous bridge’s MOSFETs. For optimal
performance, no more than 100pF parasitic capacitive load
should be present on the PWM line of ISL6609/09A
(assuming an Intersil PWM controller is used).
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. The ISL6609A’s internal
6
FN9221.1
March 6, 2006