ISL6597_06 Datasheet, PDF (6/10 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

Timing Diagram
ISL6597
PWM
UGATE
LGATE
t_PDLL
t_PDHU
t_PDLU
t_RU
2.5V
1V
t_TSSHD
t_RU
t_PTS
1V
t_PDHL
t_RL
t_TSSHD
t_FL
t_FU
t_PTS
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6597 MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t_PDLL], the lower gate begins to fall. Typical fall times [t_FL]
are provided in the Electrical Specifications. Adaptive shoot-
through circuitry monitors the LGATE voltage and turns on
the upper gate following a short delay time [t_PDHU] after the
LGATE voltage drops below ~1V. The upper gate drive then
begins to rise [t_RU] and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLU] is encountered before the upper
gate begins to fall [t_FU]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time, t_PDHL, after the upper
MOSFET’s gate voltage drops below 1V. The lower gate
then rises [t_RL], turning on the lower MOSFET. These
methods prevent both the lower and upper MOSFETs from
conducting simultaneously (shoot-through), while adapting
the dead time to the gate charge characteristics of the
MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower
MOSFET conducts for a longer time during a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
absorb the current injected into the lower gate through the
drain-to-gate (C_GD) capacitor of the lower MOSFET and
help prevent shoot through caused by the self turn-on of the
lower MOSFET due to high dV/dt of the switching node.
Tri-State PWM Input
A unique feature of the ISL6597 is the programmable PWM
logic threshold set by the control pin (VCTRL) voltage. The
VCTRL pin should connect to the controller’s VCC so that
the PWM logic thresholds follow with the VCC voltage level.
For applications using single rail 5V to power up both
controller and driver, this pin can be tied to the driver VCC,
simplifying the trace routing.
The ISL6597 also features the adaptable tri-state PWM
input. Once the PWM signal enters the shutdown window,
either MOSFET previously conducting is turned off. If the
PWM signal remains within the shutdown window for longer
than the gate turn-off propagation delay of the previously
conducting MOSFET, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. The PWM rising and falling thresholds
outlined in the Electrical Specifications determine when the
lower and upper gates are enabled. During normal operation
in a typical application, the PWM rise and fall times through
the shutdown window should not exceed either output’s turn-
off propagation delay plus the MOSFET gate discharge time
to ~1V. Abnormally long PWM signal transition times through
the shutdown window will simply introduce additional dead
time between turn off and turn on of the synchronous
bridge’s MOSFETs. For optimal performance, no more than
50pF parasitic capacitive load should be present on the
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FN9165.0
November 22, 2006