ISL6597_06 Datasheet, PDF (5/10 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6597
Electrical Specifications These specifications apply for T_A = 0°C to +70°C, unless otherwise noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 3)
t_FL
t_PDLU
t_PDLL
t_PDHU
t_PDHL
t_PTS
V_VCC = 5V, 3nF Load
V_VCC = 5V, Unloaded,
V_VCC = 5V, Unloaded,
V_VCC = 5V, Unloaded,
V_VCC = 5V, Unloaded,
V_VCC = 5V, Unloaded
-
4.0
-
18
-
25
-
18
-
23
-
30
Upper Drive Source Resistance
R_{UG_SRC} 250mA Source Current
Upper Drive Sink Resistance
R_{UG_SNK} 250mA Sink Current
Lower Drive Source Resistance
R_{LG_SRC} 250mA Source Current
Lower Drive Sink Resistance
R_{LG_SNK} 250mA Sink Current
NOTE:
3. Guaranteed by Characterization. Not 100% tested in production.
-
1.0
-
1.0
-
1.0
-
0.4
MAX
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
2.5
Ω
2.5
Ω
2.5
Ω
1.0
Ω
Functional Pin Description
PACKAGE PIN
PIN # SYMBOL
FUNCTION
1
GND Bias and reference ground. All signals are referenced to this node.
2
LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
3
PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
4
EN _{Enable input pin. Connect this pin high to enable and low to disable the driver.}
5
PGND It is the power ground return of both low gate drivers.
6
LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7
VCTRL This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for
5V PWM input.
8
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin
provides a return path for the upper gate drive.
9
UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin
and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal
Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin
and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal
Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13
PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin
provides a return path for the upper gate drive.
14
VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
15
PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation,
see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
16
PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation,
see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
17
PAD Connect this pad to the power ground plane (PGND) via thermally enhanced connection.
5
FN9165.0
November 22, 2006