ISL6532B Datasheet, PDF (6/15 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532B
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
NCH BACKFEED CONTROL
I_GATE
I_GATE
-
-0.8
-
A
-
0.8
-
A
NCH Current Sink
NCH Trip Level
VDDQ STANDBY LDO
I_NCH
V_NCH
NCH = 0.8V
-
-
6
mA
9.0 9.5 10
V
Output Drive Current
P5VSBY = 5.0V
-
-
650
mA
P5VSBY = 3.3V
-
-
550
mA
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
VREF_OUT Buffer Source Current
Maximum V_TT Load Current
R_U
-
2.5
-
kΩ
R_L
-
2.5
-
kΩ
I_{VREF_OUT}
-
-
2
mA
I_{VTT_MAX}
Periodic load applied with 30% duty cycle -3
-
3
A
and 10ms period using ISL6532EVAL1
evaluation board (see Application Note
AN1055)
VTT Over Current Trip
PGOOD
I_{TRIP_VTT}
By Design
-3.3
-
3.3
A
PGOOD Rising Threshold
PGOOD Falling Threshold
PROTECTION
V_VTTSNS/V_VDDQ S3# & S5# HIGH
V_VTTSNS/V_VDDQ S3# & S5# HIGH
- 57.5 -
%
- 45.0 -
%
VDDQ OV Level
VDDQ UV Level
Thermal Shutdown Limit
V_FB/V_REF
V_FB/V_REF
T_SD
S3# & S5# HIGH
S3# & S5# HIGH
By Design
-
115
-
%
-
85
-
%
-
140
-
°C
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6532B. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532B enters a reduced
power mode and draws less than 1mA (I_CC5) from the
5VSBY supply. This pin should be locally bypassed using a
0.1µF capacitor.
P12V (Pin 18)
P12V provides the gate drive current to the switching
MOSFETs of the PWM power stage. The V_TT regulation
circuit is also powered by P12V. P12V is only required during
S0/S1/S2 operation. P12V is typically connected to the +12V
rail of an ATX power supply.
P5VSBY (Pin 8)
This pin provides the V_DDQ output power during the S3
sleep state. The regulator is capable of providing standby
V_DDQ power from either a 5V or 3.3V source.
GND (Pin 2, 13, 21)
The GND terminals of the ISL6532B provide the return path
for the V_TT LDO, Standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible.
UGATE (Pin 20)
UGATE drives the upper (control) FET of the V_DDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
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