ISL6520B Datasheet, PDF (6/10 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6520B
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ΔV_OSC.
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2π x LO x CO
fESR= -2---_π------x-----E----S--1---R------x-----C-----O--- _{(EQ. 1)}
The compensation network consists of the error amplifier
(internal to the ISL6520B) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R₁, R₂,
R₃, C₁, C₂, and C₃) in Figure 4. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth.
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC).
3. Place 2^ND Zero at Filter’s Double Pole.
4. Place 1^ST Pole at the ESR Zero.
5. Place 2^ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
F_Z1
=
-----------------1------------------
2π x R₂ x C₁
F_Z2 = _2----π------x-----₍--R-----₁----+-1----R-----₃---₎----x-----C-----₃-
F_P1
=
---------------------------1-----------------------------
2π
x
R₂
x
⎛
⎜
⎝
C-C----_{11-----+x-----CC----2-2-⎠⎟⎞}
F_P2 = -2---_π------x-----R--1--₃------x-----C----₃-
(EQ. 2)
Figure 5 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 5. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F_P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 5 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2^/R1⁾
20LOG
0
(V_IN/ΔV_OSC)
MODULATOR
-20
GAIN
-40
F_LC
F_ESR
-60
10
100
1K
10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 5. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
6
FN9083.3
July 23, 2007