ISL6520B Datasheet, PDF (5/10 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6520B
rail, which supplies the bias voltage to the ISL6520B. If there
is nowhere for this current to go, such as to other distributed
loads on the V_CC rail, through a voltage limiting protection
device, or other methods, the capacitance on the V_CC bus
will absorb the current. This situation will allow voltage level
of the V_CC rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520B, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
V_IN
ISL6520B
UGATE
Q₁
PHASE
Q₂
LGATE
L_O
V_OUT
C_IN
C_O
RETURN
FIGURE 2. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 2 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 2 should be located as close together as possible.
Please note that the capacitors C_IN and C_O may each
represent numerous physical capacitors. Locate the ISL6520B
within 3 inches of the MOSFETs, Q₁ and Q₂. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520B must be sized to handle up to 1A peak current.
Figure 3 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/SD pin and locate the resistor,
R_OSCET close to the COMP/SD pin because the internal
current source is only 20μA. Provide local V_CC decoupling
between VCC and GND pins. Locate the capacitor, C_BOOT
as close as practical to the BOOT and PHASE pins. All
components used for feedback compensation should be
located as close to the IC a practical.
ISL6520B
BOOT
D₁
C_BOOT
PHASE
VCC
+5V
+V_IN
Q₁ L_O
Q₂
C_O
V_OUT
GND
C_VCC
FIGURE 3. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V_IN at the PHASE node. The PWM wave is smoothed by the
output filter (L_O and C_O).
OSC
PWM
COMPARATOR
DRIVER
V_IN
L_O
V_OUT
Δ V_OSC
-
+
DRIVER
PHASE _CO
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₂
C₁
R₂
Z_FB
V_OUT
Z_IN
C₃ R₃
R₁
COMP/SD
FB
-
+
ISL6520B
REFERENCE
FIGURE 4. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
5
FN9083.3
July 23, 2007