ISL6115CBZA-T Datasheet, PDF (6/13 Pages) Intersil Corporation – Power Distribution Controllers

ISL6115, ISL6116, ISL6117, ISL6120
TABLE 1. R_ISET PROGRAMMING RESISTOR VALUE
R_ISET RESISTOR
10kΩ
NOMINAL CR VTH
200mV
4.99kΩ
100mV
2.5kΩ
50mV
750Ω
15mV
NOTE: Nominal Vth = R_ISET x 20µA.
TABLE 2. C_TIM CAPACITOR VALUE
C_TIM CAPACITOR
0.022µF
NOMINAL CURRENT LIMITED
PERIOD
2ms
0.047µF
4.4ms
0.1µF
9.3ms
NOTE: Nominal time-out period = C_TIM x 93kΩ.
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10µs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
Upon a UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic or VDD
supply. This pin is a UV fault indicator. For an OC
latch-off indication, monitor CTIM, pin 6. This pin will
rise rapidly from 1.9V to VDD once the time-out period
expires.
See Figures 12 through 16 for waveforms relevant to
text.
The IC is reset after an OC latch-off condition by a low
level on the PWRON pin and is turned on by the
PWRON pin being driven high.
Application Considerations
Design applications where the CR Vth is set extremely
low (25mV or less), there is a two-fold risk to
consider.
• There is the susceptibility to noise influencing the
absolute CR Vth value. This can be addressed with a
100pF capacitor across the R_SENSE resistor.
• Due to common mode limitations of the
overcurrent comparator, the voltage on the ISET
pin must be 20mV above the IC ground either
initially (from I_SET*R_SET) or before C_TIM reaches
time-out (from gate charge-up). If this does not
happen, the IC may incorrectly report overcurrent
fault at start-up when there is no fault. Circuits
with high load capacitance and initially low load
current are susceptible to this type of unexpected
behavior.
Do not signal nor pull-up the PWRON input to > 5V.
Exceeding 6V on this pin will cause the internal charge
pump to malfunction.
During the soft-start and the time-out delay duration
with the IC in its current limit mode, the V_GS of the
6
external N-Channel MOSFET is reduced driving the
MOSFET switch into a (linear region) high r_DS(ON)
state. Strike a balance between the CR limit and the
timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or
destroyed due to excessive internal power dissipation.
Refer to the MOSFET SOA information in the
manufacturer’s data sheet.
When driving particularly large capacitive loads a
longer soft-start time to prevent current regulation
upon charging and a short CR time may offer the best
application solution relative to reliability and FET MTF.
Physical layout of R_SENSE resistor is critical to
avoid the possibility of false overcurrent occurrences.
Ideally, trace routing between the R_SENSE resistors
and the IC is as direct and as short as possible with
zero current in the sense lines (see Figure 1)..
CORRECT
INCORRECT
TO ISEN AND
R_ISET
CURRENT
SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
Using the ISL6116 as a -48V
Low Side Hot Swap Power
Controller
To supply the required V_DD, it is necessary to maintain
the chip supply 10V to 16V above the -48V bus. This
may be accomplished with a suitable regulator
between the voltage rail and pin 5 (VDD). By using a
regulator, the designer may ignore the bus voltage
variations. However, a low-cost alternative is to use a
Zener diode (see Figure 2 for typical 5A load control);
this option is detailed in the following.
Note that in this configuration the PGOOD feature
(pin 7) is not operational as the I_SEN pin voltage is
always < UV threshold.
See Figures 17 through 20 for waveforms relevant to
-48V and other high voltage applications.
FN9100.7
April 29, 2010