ISL6115CBZA-T Datasheet, PDF (5/13 Pages) Intersil Corporation – Power Distribution Controllers

ISL6115, ISL6116, ISL6117, ISL6120
Electrical Specifications
V_DD = 12V, T_A = T_J = 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
PWRON Pull-Up Voltage
PWRN_V
PWRON Pin Open
2.7
3.2
-
V
PWRON Rising Threshold
PWR_Vth
1.4
1.7
2.0
V
PWRON Hysteresis
PWR_hys
130
170
250
mV
PWRON Pull-Up Current
PWRN_I
9
17
25
µA
CURRENT REGULATION DURATION/POWER GOOD
C_TIM Charging Current
C_TIM Fault Pull-Up Current (Note 6)
Current Limit Time-Out Threshold
Voltage
C_TIM_ichg0
V_CTIM = 0V
C_TIM_Vth
CTIM Voltage
16
20
23
µA
-
20
-
mA
1.3
1.8
2.3
V
Power Good Pull Down Current
PG_Ipd
V_OUT = 0.5V
-
8
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
-
mA
Description and Operation
The members of this IC family are single power supply
distribution controllers for generic hot swap
applications across the +2.5V to +12V supply range.
The ISL6115 is targeted for +12V switching
applications whereas the ISL6116 is targeted for +5V,
the ISL6117 for +3.3V and the ISL6120 for +2.5V
applications. Each IC has a hardwired undervoltage
(UV) threshold level approximately 17% lower than the
stated voltages.
These ICs feature a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turnHon ramp all set with a minimum of external
passive components. The ICs also include severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, the ICs
have a UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden in-rush
current.
At turn-on, the external gate capacitor of the N-
Channel MOSFET is charged with a 10µA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115 charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~V_DD +5V, for the other three ICs the gate
drive voltage is limited to the chip bias voltage, VDD.
Load current passes through the external current
sense resistor. When the voltage across the sense
resistor exceeds the user programmed CR voltage
threshold value, (see Table 1 for R_ISET programming
resistor value and resulting nominal current
regulation threshold voltage, V_CR) the controller
enters its current regulation mode. At this time, the
time-out capacitor, on CTIM pin is charged with a
20µA current source and the controller enters the
current limit time to latch-off period. The length of the
current limit time to latch-off duration is set by the
value of a single external capacitor (see Table 2) for
C_TIM capacitor value and resulting nominal current
limited time-out to latch-off duration placed from the
CTIM pin (pin 6) to ground. The programmed current
level is held until either the OC event passes or the
time-out period expires. If the former is the case then
the N-Channel MOSFET is fully enhanced and the C_TIM
capacitor is discharged. Once C_TIM charges to 1.87V
signaling that the time-out period has expired, an
internal latch is set whereby the FET gate is quickly
pulled to 0V turning off the N-Channel MOSFET
switch, isolating the faulty load.
5
FN9100.7
April 29, 2010