ISL54228 Datasheet, PDF (6/17 Pages) Intersil Corporation – High-Speed USB 2.0 (480Mbps) DPST Switch with Overvoltage Protection (OVP)

ISL54228
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: V_DD = +3.3V, GND = 0V, V_LP = GND,
V_OEH = 1.4V, V_OEL = 0.5V, (Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
Positive Supply Current, I_DD V_DD = 3.6V, OE = 1.4V, LP = GND
25
-
25
32
µA
Full
-
-
38
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V_OEL, V_LPL V_DD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, V_OEH, V_LPH V_DD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, V_OEL, V_LPL V_DD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High, V_OEH, V_LPH V_DD = 3.7V to 4.2
Full
1.7
-
-
V
Input Voltage Low, V_OEL, V_LPL V_DD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, V_OEH, V_LPH V_DD = 4.3V to 5.25V
Full
2.0
-
-
V
Input Current, I_OEL, I_LPL
V_DD = 5.25V, OE = 0V, LP = 0V
Full
-
-8.2
-
nA
Input Current, I_OEH, I_LPH
V_DD = 5.25V, OE = 5.25V, LP = 5.25V, Full
-
1.4
-
µA
4MΩ Pull-down
NOTES:
9. V_LOGIC = Input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
13. r_ON matching between channels is calculated by subtracting the channel with the highest max r_ON value from the channel
with lowest max r_ON value.
14. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
LOGIC
INPUT
VDD
0V
SWITCH
INPUT
V_INPUT
SWITCH
OUTPUT
0V
50%
t_OFF
V_OUT
90%
t_ON
t_r < 20ns
t_f < 20ns
90%
V_DD
C
V_INPUT
SWITCH
INPUT
COMx
OE
VIN
GND
Dx
V_OUT
R_L
C_L
50Ω 50pF
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V _(INPUT)
---------^R-----^L---------
R_L + r_ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6
FN7628.0
July 29, 2010