ISL54066_0911 Datasheet, PDF (6/14 Pages) Intersil Corporation – Negative Signal Swing, High Off-Isolation, Dual SPST Single Supply Switch

ISL54066
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, V_{CTL_H} = 1.0V, V_{CTL_L} = 0.4V (Note 9),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t_ON
V+ = 1.8V, V_IN = 1.8V, R_L = 50Ω, C_L = 35pF
25
-
180
-
ns
(See Figure 1)
Turn-OFF Time, t_OFF
V+ = 1.8V, V_IN = 1.8V, R_L = 50Ω, C_L = 35pF
25
-
44
-
ns
(See Figure 1)
Charge Injection, Q
C_L = 1.0nF, V_G = 0V, R_G = 0Ω, (See Figure 2)
25
-3dB Bandwidth
V_COM = 1V_RMS, R_L = 50Ω, C_L = 5pF
25
INx OFF Capacitance, C_OFF
f = 1MHz, GND1 = float (See Figure 6)
25
OUTx ON Capacitance, C_OUT(ON) f = 1MHz, GND2 = float (See Figure 6)
25
DIGITAL INPUT CHARACTERISTICS
-
40
-
-
30
-
-
33
-
-
124
-
pC
MHz
pF
pF
Input Voltage Low, V_{CTLx_L}
Input Voltage High, V_{CTLx_H}
Input Current, I_{CTLx_H}, I_{CTLx_L}
V+ = 2.0V, V_CTLx = 0V or V+
25
-
-
0.4
V
25
1.0
-
-
V
25
-0.5
-
-
µA
Full
-
0.5
-
µA
NOTES:
9. V_{CTL_x} = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
13. r_ON matching between channels is calculated by subtracting the channel with the highest max r_ON value from the channel with lowest max r_ON
value, between IN1 and IN2.
14. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V+
LOGIC
INPUT
0V
SWITCH
INPUT
V_IN
SWITCH
OUTPUT _0V
50%
t_OFF
V_OUT
90%
t_ON
t_r < 5ns
t_f < 5ns
90%
V+
C
SWITCH
INPUT
LOGIC
INPUT
IN
CTL
OUT
GNDx
V_OUT
R_L
C_L
50Ω 35pF
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V _(IN)
---------^R----^L----------
R_L + r_ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
6
FN6584.1
November 3, 2009