ISL54056_07 Datasheet, PDF (6/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch

ISL54056
Test Circuits and Waveforms
V+
LOGIC
INPUT
0V
SWITCH
INPUT
V_NO
SWITCH
OUTPUT _0V
50%
t_OFF
V_OUT
90%
t_ON
90%
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO or NC
IN
GND
COM
V_OUT
R_L
C_L
50Ω 35pF
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
---------^R-----^L---------
R_L + r_ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
V_OUT
LOGIC ^ON
INPUT
ΔV_OUT
OFF
Q = ΔV_OUT x C_L
V+
ON
0V
R_G
NO or NC
COM
V_G
GND
IN
LOGIC
INPUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V_OUT
C_L
V+
C
V+
LOGIC
INPUT
0V
SWITCH
OUTPUT
V_{OUT 0V}
NO
V_NX
NC
IN
COM
V_OUT
R_L
C_L
50Ω
35pF
90%
LOGIC
INPUT
GND
t_D
C_L includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6357.4
August 15, 2007