ISL34341 Datasheet, PDF (6/11 Pages) Intersil Corporation – WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel

ISL34341
Pin Descriptions (Continued)
DESCRIPTION
PIN NUMBER
PIN NAME
SERIALIZER
DESERIALIZER
49
VIDEO_TX
29, 30
31 to 34
35
SCL, SDA
I2CA[3:0]
MASTER
CMOS input for video flow direction
1: video serializer
0: video deserializer
I²C Interface Pins (I²C DATA, I²C CLK)
I²C Device Address
I²C Master Mode
1: Master
0: Slave
16
RSTB/PDB
CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When
this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode.
14
STATUS
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: otherwise
Note: serializer and deserializer switch roles during side-channel reverse traffic
36
REF_RES
Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
27
GND_P
PLL Ground
48, 64
GND_IO
Digital (Parallel and Control) Ground
44, 45
GND_CDR
Analog (Serial) Data Recovery Ground
39, 42
GND_TX
Analog (Serial) Output Ground
37
GND_AN
Analog Bias Ground
17, 18
GND_CR
Core Logic Ground
19, 20
VDD_CR
Core Logic VDD
43
VDD_TX
Analog (Serial) Output VDD
38
VDD_AN
Analog Bias VDD
46, 47
VDD_CDR
Analog (Serial) Data Recovery VDD
1, 50
VDD_IO
Digital (Parallel and Control) VDD
28
VDD_P
PLL VDD
15
TEST_EN
Must be connected to ground
Exposed Pad Exposed Pad
Must be connected to ground
NOTES:
3. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external
components or features.
4. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are
provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they
should be considered a common connection.
6
FN6827.1
October 8, 2010