ISL3179E Datasheet, PDF (6/17 Pages) Intersil Corporation – High ESD Protected, +125°C, 40Mbps 3.3V, Full Fail-Safe, RS-485/RS-422 Transceivers

ISL3179E, ISL3180E
Electrical Specifications Test Conditions: V_CC = 3.0V to 3.6V; Typicals are at V_CC = 3.3V, T_A = +25°C. (Note 3) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 13) TYP (Note 13) UNITS
Receiver Enable to Output Low
t_ZL R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6),
Full
(Note 7)
-
11
15
ns
Receiver Disable from Output High t_HZ R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6)
Full
Receiver Disable from Output Low t_LZ R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6)
Full
Time to Shutdown
t_SHDN (Note 8)
Full
Receiver Enable from Shutdown to t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6),
Full
Output High
(Notes 8, 10)
-
10
15
ns
-
10
15
ns
60
-
600
ns
-
-
1000
ns
Receiver Enable from Shutdown to t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6),
Full
-
-
1000
ns
Output Low
(Notes 8, 10)
NOTES:
3. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
4. Supply current specification is valid for loaded drivers when DE = 0V.
5. Applies to peak current. See “Typical Performance Curves” on page 11 for more information.
6. Because of the shutdown feature, keep RE = 0 to prevent the device from entering SHDN.
7. Because of the shutdown feature, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
8. These IC’s are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not
to enter shutdown. If the inputs are in this state for at least 700ns, the parts are guaranteed to have entered shutdown. See “Low Power
Shutdown Mode” on page 10.
9. Keep RE = V_CC, and set the DE signal low time >700ns to ensure that the device enters SHDN.
10. Set the RE signal high time >700ns to ensure that the device enters SHDN.
11. This is the part-to-part skew between any two units tested with identical test conditions (Temperature, V_CC, etc.).
12. V_CC = 3.3V ±5%
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
R_L = 60Ω
V_CM
-7V TO +12V
375Ω
FIGURE 1A. V_OD AND V_OC
FIGURE 1B. V_OD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
6
FN6365.2
April 22, 2008